Hyundai Motor Company

Kia Motors Corporation

Kia Corporation

Hyundai Autron Company Ltd.

Dae Hwan Chun

Youngkyun Jung

Jong Seok Lee

Junghee Park

Kyoung-Kook Hong

NackYong Joo

Jungyeop Hong

Jongseok Lee

Hyun Woo Noh

JongSeok Lee

Su Bin Kang

Nack Yong Joo

Youngjoon Kim

Hyuk Woo

Taeyeop Kim

Nackyong Joo

A method for manufacturing a semiconductor device includes forming an N-type layer on the first surface of the N+ type substrate, etching the N-type layer to form a trench, forming a sacrificial layer on an inner bottom surface of the trench, forming a first mask on an inner side of the trench, removing the sacrificial layer, and forming a P type shield region by implanting ions into an inner surface of the trench exposed by the removal of the sacrificial layer.

Method for manufacturing semiconductor device and semiconductor device manufactured thereby

Provided is a semiconductor device including a semiconductor substrate, a plurality of gate electrodes disposed on the upper surface portion of the semiconductor substrate and spaced apart from each other, a plurality of emitter electrodes disposed to be overlapped with each of the plurality of gate electrodes, and a collector electrode disposed on the lower surface of the semiconductor substrate.

Semiconductor device and three-phase inverter comprising the same

A semiconductor device includes an N+ type substrate, an N− type layer disposed on a first surface of the N+ type substrate and having a trench opened to a surface opposite to the surface facing the N+ type substrate, a P type region disposed in the N− type layer and disposed on a side surface of the trench, a gate electrode disposed in the trench, and a source electrode and a drain electrode insulated from the gate electrode. The N− type layer includes a P type shield region covering a bottom surface and an edge of the trench.

Semiconductor device and method of manufacturing the same

Disclosed is a semiconductor module including a substrate, a first semiconductor layer positioned on the substrate, an insulator positioned in a partial region on the first semiconductor layer, a second semiconductor layer positioned on the insulator, a first semiconductor device formed on the first semiconductor layer, and a second semiconductor device formed on the second semiconductor layer, wherein one of the first semiconductor layer and the second semiconductor layer includes gallium oxide (GaO) and the other includes silicon (Si).

Semiconductor module and method for manufacturing the same

A semiconductor device includes an n− type layer on a first surface of the substrate, a p type region on a part of the n− type layer, a gate on the n− type layer and the p type region, a first gate protection layer on the gate and a second gate protection layer on the first gate protection layer, a source on the second gate protection layer and the p type region, and a drain on the second surface of the substrate.

An embodiment semiconductor module includes a substrate, a heterogeneous thin film including a first semiconductor layer disposed on a first region of the substrate and a second semiconductor layer disposed on a second region of the substrate, a first semiconductor device disposed on the first semiconductor layer of the heterogeneous thin film, and a second semiconductor device disposed on the second semiconductor layer of the heterogeneous thin film, wherein one of the first semiconductor layer or the second semiconductor layer comprises gallium oxide (GaO) and the other includes silicon (Si).

A semiconductor device according to an exemplary embodiment of the present disclosure includes a substrate, an n&#x2212; type layer, a plurality of trenches, a p type region, a p+ type region, an n+ type region, a gate electrode, a source electrode, and a drain electrode. The semiconductor device may include a plurality of unit cells. A unit cell among the plurality of unit cells may include a contact portion with which the source electrode and the n+ type region are in contact, a first branch part disposed above the contact portion on a plane, and a second branch part disposed below the contact portion on a plane, the plurality of trenches are separated from each other and disposed with a stripe shape on a plane.

Semiconductor device

A Schottky barrier diode includes: an n&#x2212; type layer disposed on a first surface of an n+ type silicon carbide substrate; a p+ type region and a p type region disposed on the n&#x2212; type layer and separated from each other; an anode disposed on the n&#x2212; type layer, the p+ type region, and the p type region; and a cathode disposed on a second surface of the n+ type silicon carbide substrate. The p type region is in plural, has a hexagonal shape on the plane, and is arranged in a matrix shape, and the n&#x2212; type layer disposed between the p+ type region and the p type region has a hexagonal shape on the plane and encloses the p type region.

Schottky barrier diode and method of manufacturing the same

A semiconductor device may include: an n type of layer disposed on a first surface of a substrate; a p+ type of region disposed on the first surface of the substrate; a p&#x2212; type of region disposed at a top portion of the n type of layer; a first electrode disposed on the p+ type of region and the p&#x2212; type of region; and a second electrode disposed on a second surface of the substrate, wherein the side surface of the p+ type of region and the side surface of the n type of layer are in contact, and the thickness of the p+ type of region is the same as the thickness of the n type of layer and the thickness of the p&#x2212; type of region.

A semiconductor device is provide. The device includes a first n&#x2212; type of layer, a second n&#x2212; type of layer, and an n+ type of region sequentially disposed on a first surface of a substrate. A trench is disposed on a side surface of the second n&#x2212; type of layer, a p type of region is disposed between the second n&#x2212; type of layer and the trench, and a gate electrode is disposed on a bottom surface of the trench. A source electrode is disposed on the n+ type of region and a drain electrode is disposed on a second surface of the substrate. The second n&#x2212; type of layer includes a first concentration layer, a second concentration layer, a third concentration layer, and a fourth concentration layer sequentially disposed on the first n&#x2212; type of layer.

A semiconductor device includes: an n+ type of silicon carbide substrate, an n&#x2212; type of layer, first trenches, a p type of region, a p+ type of region, an n+ type of region, a gate electrode, a source electrode, and a drain electrode. The semiconductor device may include a plurality of unit cells, wherein one of the plurality of unit cells may include a contact portion at which the source electrode and the p+ type of region contact each other, an outer portion disposed at upper and lower portions of the contact portion in a plan view, and a connection portion connecting the contact portion to the outer portion, a width between the first trenches horizontally adjacent in the plan view in the contact portion is equal to a width between the first trenches horizontally adjacent in the plan view in the outer portion, and a width between the first trenches horizontally adjacent in the plan view in the connection portion is less than a width between the first trenches horizontally adjacent in the plan view in the contact portion.

Semiconductor device including silicon carbide

A semiconductor device is provided and includes an n&#x2212; type layer disposed at a substrate first surface. A trench, n type region, and p+ type region are disposed on the n&#x2212; type layer. A p type region is disposed on the n type region. An n+ type region is disposed on the p type region. A gate insulating layer is disposed in the trench. A gate electrode is disposed on the gate insulating layer. A source electrode is disposed on an insulating layer disposed on the gate electrode, n+ type region, and p+ type region. A drain electrode is disposed at a substrate second surface. The n type region includes a first portion contacting the trench side surface and extending parallel to a substrate upper surface and a second portion contacting the first portion, separated from the trench side surface, and extending vertical to the substrate upper surface.

Semiconductor device and method manufacturing the same

The present disclosure provides a semiconductor device including a substrate, an n&#x2212; type layer, an n+ type region, a p type region, a p+ type region, a gate insulating layer, a gate electrode, a source electrode, and a drain electrode, wherein the n+ type region is disposed at a left side and a right side of the n&#x2212; type layer in a plan view and configured to form in a striped pattern in a plan view, wherein the p+ type region is disposed at an outer surface of the n+ type region in a plan view and configured to form in a striped pattern in a plan view, wherein the p type region is disposed at an inner surface the n+ type region in a plan view and is separated by a predetermined interval along a longitudinal direction of the n+ type region in a plan view.

A semiconductor device includes an n+ type silicon carbide substrate, an n&#x2212; type layer, an n type layer, a plurality of trenches, a p type region, an n+ type region, a gate insulating film, a gate electrode, a source electrode, a drain electrode, and a channel. The plurality of trenches is disposed in a planar matrix shape. The n+ type region is disposed in a planar mesh type with openings, surrounds each of the trenches, and is in contact with the source electrode between the trenches adjacent to each other in a planar diagonal direction. The p type region is disposed in the opening of the n+ type region in a planar mesh type.

Semiconductor device and method for manufacturing same

A semiconductor device is provided. The semiconductor device includes a n&#x2212; type layer disposed at a first surface of a n+ type silicon carbide substrate and a trench disposed at the n&#x2212; type layer. Additionally, a first gate electrode and a second gate electrode are disposed in the trench and separated from each other. A source electrode is insulated from the first gate electrode and the second gate electrode. Further, the semiconductor includes a drain electrode that is disposed at a second surface of the n+ type silicon carbide substrate, a first channel disposed adjacent to a side surface of the trench and a second channel disposed under the lower surface of the trench. The first channel and the second channel are separated from each other.

Growing community of inventors

Gwangmyeong-si, South Korea

Dae Hwan Chun