Skhynix Inc.

Dae Ho Yun

Jae Woo Lee

Jun Hyun Chun

Jin Il Chung

Jin Wook Burm

A semiconductor device including a test circuit is disclosed. The semiconductor device includes a test pad coupled to a probe of a test device during a wafer test; a normal pad configured to receive a power or a signal during a normal mode; and a test circuit configured to perform a predetermined test operation based on a test signal received through the test pad. The test circuit is disposed below the normal pad.

Semiconductor device including test circuit

A semiconductor memory apparatus may include a control circuit, a decoding circuit, and a memory circuit. The control circuit may output one of bank group signals as either a first bank group distribution signal or a second bank group distribution signal and output one of data designation addresses as either a first data designation distribution address or a second data designation distribution address, in response to a first test signal and a second test signal. The decoding circuit may generate decoding signals depending on remaining bank group signals, remaining data designation addresses, bank designation signals, the first and second bank group distribution signals, and the first and second data designation distribution addresses. The memory may select certain memory location to output or store data, in response to the decoding signals.

Semiconductor memory apparatus

A data storage circuit includes a first antifuse which is programmed in response to a first access signal, and provide data indicating whether the first antifuse is programmed to a data node, an initialization section which controls a voltage level of the data node in response to an initialization flag, and a second antifuse which is programmed in response to the first access signal, and provide the initialization flag indicating whether the second antifuse is programmed to the initialization section.

Data storage circuit and system including the same

A semiconductor memory apparatus includes a DBI calculation block, an inversion latch block, an inverted data selective output block, and a pipe latch block. The DBI calculation block performs a DBI calculation and outputs a DBI result signal based on a result of the DBI calculation. The inversion latch block inverts data and outputs the inverted data when a DBI enable signal is enabled. The inverted data selective output block outputs the inverted data as a data inversion signal in response to the DBI result signal and a pipe input signal. The pipe latch block receives the data, which is not inverted, and the inverted data, and outputs one of the data and the inverted data according to the result of the DBI calculation.

Semiconductor memory apparatus and system including the same

A rail-to-rail comparator including a first comparison unit connected to a first terminal and configured to compare differential input signals to differential reference voltages; a second comparison unit connected to a second terminal and configured to compare the differential input signals to the differential reference voltages; and an output unit configured to be driven in response to a clock signal and to generate a complementary output signal according to comparison results of the first and second comparison units.

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Icheon-si, South Korea

Dae Ho Yun