Skhynix Inc.

Dae Ho Ra

Byung Kuk Yoon

Min Sik Han

Hong Gyeom Kim

A semiconductor device includes a latch control circuit configured to generate a latch input signal, which is enabled in response to a latency signal, and configured to generate a latch output signal, which is enabled in response to an order control signal. The semiconductor device also includes a pipe latch circuit configured to latch input data in response to a pipe input signal and configured to output the latched input data as latch data in response to a pipe output signal. The semiconductor device additionally includes a data output circuit configured to latch the latch data in response to the latch input signal and configured to output the latched latch data as output data in response to the latch output signal, wherein the output data is outputted by performing an alignment operation for the latch data in response to the latch output signal.

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Seoul, South Korea

Dae Ho Ra