Hynix Semiconductor Inc.

Hyundai Electronics Industries Co. Ltd.

Dae Gyu Park

Heung Jae Cho

Kwan Yong Lim

In Seok Yeo

Tae Ho Cha

Se Aug Jang

Tae Kyun Kim

Jin Sang Park

A method for forming a metal gate capable of preventing degradation in a characteristic of a gate insulating film upon formation of the metal gate. The method of forming the metal gate comprises the steps of providing a silicon substrate having device isolation films of a trench shape for defining an active region; forming a gate insulating film on the surface of the silicon substrate by means of a thermal oxidization process; sequentially forming a barrier metal film and a metal film for the gate on the gate insulating film; and patterning the metal film for the gate, the barrier metal film and the gate insulating film, wherein deposition of the barrier metal film and the metal film for the gate is performed by means of an atomic layer deposition (ALD) process or remote plasma chemical vapor deposition (CVD) process.

Method of forming a metal gate in a semiconductor device using atomic layer deposition process

The present invention discloses the single gate CMOS with the surface channel manufactured according to the manufacturing method of the present invention is very advantageous for improving the characteristics, yield and reliability of the device, by performing decoupled plasma nitridation (DPN) process on the gate oxide film of the cell NMOS and the peripheral PMOS, respectively, thereby forming a silicon nitride on the surface of the gate oxide film. Further, the single gate CMOS with the surface channel can be formed more easily through the simplified process in overall, without requiring a separate transient ion implantation process, even when the gate electrode of the n polysilicon layer is used, by having the threshold voltage of the cell NMOS be approximately &plus;0.9V, the threshold voltage of the peripheral PMOS be approximately &minus;0.5V and above, and the threshold voltage of the peripheral NMOS be approximately &plus;0.5V and below. In addition, since the cell NMOS already has &plus;0.9V of threshold voltage, back bias does not have to be applied separately to achieve the &plus;0.9V threshold voltage, and the device with low power consumption is formed successfully.

CMOS of semiconductor device and method for manufacturing the same

CMOS device arrangements have a surface channel, and a method for manufacturing the same by forming a multi-layer that includes a first metal layer, a polysilicon layer and a second metal layer having a work function from 4.8 through 5.0 eV on a cell region NMOS and a gate electrode of a peripheral circuit region PMOS, and by forming a multi-layer that includes a polysilicon layer and a second metal layer on a gate electrode of a peripheral circuit region NMOS. Because of the multi-layered gate electrode, a separate transient ion implantation process is not necessary, which consequently simplified the CMOS manufacturing process, while maintaining the threshold voltage of each peripheral circuit region &minus;0.5V and below, and the threshold voltage of the peripheral circuit region NMOS &plus;0.5V and below. Meantime, since the cell NMOS has the threshold voltage of &plus;1V thanks to the first metal layer, no separate back bias is necessary, thereby forming a device with low power consumption, which consequently improves characteristics, yield and reliability of the device.

Cmos of semiconductor device and method for manufacturing the same

There is disclosed a method of forming a gate electrode in a semiconductor device. The present invention forms a gate insulating film using (TiO ) (Al O ) in which a titanium oxide film (TiO ) having a high dielectric constant and an aluminum oxide film having leakage and interfacial property are mixed. Therefore, the present invention could not only improve the leakage current characteristic of a semiconductor device but also early develop a high-speed device having a high density in the future.

Method of forming a gate electrode in a semiconductor device

A method of manufacturing semiconductor devices forms a surface channel CMOSFET in the process of manufacturing a metal gate. The method forms a (Ti Al ) N film (where z ranges from about 0.0 to about 0.2) having a work function value ranging from about 4.2 to about 4.3 eV on a gate insulating film in a nMOS region, a (Ti Al ) N film (where z ranges from about 0.3 to about 0.6) having a work function value ranging from about 4.8 to about 5.0 eV on the gate insulating film in a pMOS region, thus implementing a surface channel CMOS device both in the nMOS region and the pMOS region. Therefore, the threshold voltage is reduced.

Method of manufacturing semiconductor devices with titanium aluminum nitride work function

The present invention discloses a method for forming a gate for semiconductor devices by depositing a TaO N film as a gate oxide film. The method includes the steps of providing a semiconductor substrate where a device isolation film has been formed, growing an SiO or SiON film on the semiconductor substrate, depositing an amorphous TaO N film on the SiO or SiON film, performing a low temperature annealing process to improve quality of the amorphous TaO N film, performing a high temperature annealing process ex-situ to remove organic substances and nitrogen in the amorphous TaO N film, and crystallize the amorphous TaO N film, and depositing a metal barrier film on the crystallized TaO N film, and depositing a polysilicon film or metal film for a gate electrode on the metal barrier film.

Method for forming a gate for semiconductor devices

There is disclosed a method of manufacturing a semiconductor device utilizing a gate dielectric film. The present invention can obtain a (Al O ) &mdash;(TiO ) gate dielectric film where its the dielectric constant is higher than that of Al O and its leakage current characteristic is improved compared to TiO , by depositing a Ti Al N film on a semiconductor substrate and then forming the (Al O ) &mdash;(TiO ) gate dielectric film by oxidization process. Therefore, the present invention can implement a high-speed high-density logic device and an ultra high integration device of more than 1G DRAM class, which utilize a high dielectric material as the gate dielectric film.

Growing community of inventors

Kyoungki-do, South Korea

Dae Gyu Park