International Business Machines Corporation

Globalfoundries Inc.

Freescale Semiconductor,inc.

Chartered Semiconductor Manufacturing Ltd (corporation)

Infineon Technologies Ag

Advanced Micro Devices Corporation

Infineon Technologies North America Corp.

Dae-Gyu Park

Kevin K Chan

Min Yang

Oleg Gluschenkov

Xinhui Wang

Young-Hee Kim

Effendi Leobandung

Michael Patrick Chudzik

Jinghong Li

Vijay Narayanan

Vamsi Krishna Paruchuri

Haizhou Yin

Masaharu Kobayashi

Ghavam G Shahidi

Xiangdong Chen

Naim Moumen

Devendra K Sadana

Tak H Ning

Judson Robert Holt

Deborah A Neumayer

Bahman Hekmatshoar-Tabari

Christopher Peter D'Emic

Rashmi Jha

Weipeng Li

Pouya Hashemi

Jack Allan Mandelman

Ramachandra Divakaruni

Davood Shahrjerdi

Zhijiong Luo

Jin Cai

Yun-Yu Wang

Kwong Hon Wong

Abhishek Dube

Kenneth Jay Stein

Zhibin Ren

Thomas Safron Kanarsky

Michael Abramovich Gribelyuk

Marinus Hopstaken

Melanie J Sherony

Zhengmao Zhu

Huilong Zhu

Bahman Hekmatshoartabari

Alfred Grill

Isaac Lauer

Cyril Cabral, Jr

Jeffrey Bowman Johnson

Herbert Lei Ho

Martin Michael Frank

Ravikumar Ramachandran

Babar Ali Khan

Ramachandran Muralidhar

Siddarth A Krishnan

Viorel C Ontalus

Voon-Yew Thean

Jin-Ping Han

Qi Zhang

Yong Meng Lee

Uzma B Rana

Yue Ke

Laegu Kang

Hyungjun Kim

Norma Edith Sosa

Marinus J P Hopstaken

Joseph S Newbury

Mark J Hurley

Christine Qiqing Ouyang

Amanda L Tessier

Annie Levesque

Tsong-Lin Tai

Carl John Radens

Theodorus E Standaert

Shom Ponoth

Ying Di Zhang

Fei Liu

Dominic Joseph Schepis

Jeng-Bang Yau

Cheng-Wei Cheng

Laertis Economikos

Brian Joseph Greene

Renee Tong Mo

Sufi Zafar

Qiqing Christine Ouyang

Barry P Linder

Michael P Belyansky

Rama Divakaruni

Alessandro Cesare Callegari

Leathen Shi

William J Cote

Deok-Kee Kim

Jun Yuan

Da Zhang

Anda C Mocuta

Wenjuan Zhu

Young Way Teh

Frank Bin Yang

Kevin McStay

Qingyun Yang

Christopher V Baiocco

Helen Wang

Akihisa Sekiguchi

A method of forming a semiconductor material of a photovoltaic device that includes providing a surface of a hydrogenated amorphous silicon containing material, and annealing the hydrogenated amorphous silicon containing material in a deuterium containing atmosphere. Deuterium from the deuterium-containing atmosphere is introduced to the lattice of the hydrogenated amorphous silicon containing material through the surface of the hydrogenated amorphous silicon containing material. In some embodiments, the deuterium that is introduced to the lattice of the hydrogenated amorphous silicon containing material increases the stability of the hydrogenated amorphous silicon containing material.

Method of stabilizing hydrogenated amorphous silicon and amorphous hydrogenated silicon alloys

A semiconductor fin including a single crystalline semiconductor material is formed on a dielectric layer. A semiconductor shell including an epitaxial semiconductor material is formed on all physically exposed surfaces of the semiconductor fin by selective epitaxy, which deposits the semiconductor material only on semiconductor surfaces and not on dielectric surfaces. The epitaxial semiconductor material can be different from the single crystalline semiconductor material, and the semiconductor shell can be bilaterally strained due to lattice mismatch. A fin field effect transistor including a strained channel can be formed. Further, the semiconductor shell can advantageously alter properties of the source and drain regions, for example, by allowing incorporation of more dopants or by facilitating a metallization process.

Fin field effect transistor including a strained epitaxial semiconductor shell

An approach to providing a method of forming a dopant junction in a semiconductor device. The approach includes performing a surface modification treatment on an exposed surface of a semiconductor layer and depositing a dopant material on the exposed surface of the semiconductor layer. Furthermore, the approach includes alloying a metal layer with a dopant layer to form a semiconductor device junction where the semiconductor layer is composed of a Group III-V semiconductor material, the surface modification treatment occurs in a vacuum chamber to remove surface oxides from the exposed surface of the semiconductor layer, and each of the above processes occur at a low temperature.

Selective dopant junction for a group III-V semiconductor device

Embodiments of the present invention provide semiconductor structures and methods for making the same that include a boron nitride (BN) spacer on a gate stack, such as a gate stack of a planar FET or FinFET. The boron nitride spacer is fabricated using atomic layer deposition (ALD) and/or plasma enhanced atomic layer deposition (PEALD) techniques to produce a boron nitride spacer at relatively low temperatures that are conducive to devices made from materials such as silicon (Si), silicon germanium (SiGe), germanium (Ge), and/or III-V compounds. Furthermore, the boron nitride spacer may be fabricated to have various desirable properties, including a hexagonal textured structure.

Low temperature spacer for advanced semiconductor devices

At least one dielectric pad layer is formed on a semiconductor-on-insulator (SOI) substrate. A deep trench is formed in the SOI substrate, and a combination of an outer electrode, a node dielectric, and an inner electrode are formed such that the top surface of the inner electrode is recessed below the top surface of a buried insulator layer of the SOI substrate. Selective epitaxy is performed to fill a cavity overlying the inner electrode with an epitaxial semiconductor material portion. A top semiconductor material layer and the epitaxial semiconductor material portion are patterned to form a fin structure including a portion of the top semiconductor material layer and a portion of the epitaxial semiconductor material portion. The epitaxial semiconductor material portion functions as a conductive strap structure between the inner electrode and a semiconductor device to be formed on the fin structure.

Integrated fin and strap structure for an access transistor of a trench capacitor

Ion implantation to change an effective work function for dual work function metal gate integration is presented. One method may include forming a high dielectric constant (high-k) layer over a first-type field effect transistor (FET) region and a second-type FET region; forming a metal layer having a first effective work function compatible for a first-type FET over the first-type FET region and the second-type FET region; and changing the first effective work function to a second, different effective work function over the second-type FET region by implanting a species into the metal layer over the second-type FET region.

Changing effective work function using ion implantation during dual work function metal gate integration

Method of forming integrated fin and strap structure for an access transistor of a trench capacitor

A method for fabricating a semiconductor device includes receiving a finned substrate comprising an isolation layer with a plurality of semiconductor fins formed thereon, forming a gate structure over a fin that comprises a gate and a seed layer disposed below the gate and immediately adjacent to the fin, and epitaxially growing a gate extender from the seed layer that laterally extends over a source or drain region of the fin. In one embodiment, a semiconductor device includes a finned substrate comprising an isolation layer with a plurality of semiconductor fins formed thereon, a gate structure formed over a fin of the plurality of fins, the gate structure comprising a gate and a seed layer disposed below the gate and immediately adjacent to the fin, and a gate extender epitaxially grown from the seed layer that laterally extends over a source or drain region of the fin.

Shallow extension junction

An approach to providing a method of forming a dopant junction in a semiconductor device. The approach includes performing a surface modification treatment on an exposed surface of a semiconductor layer and depositing a dopant material on the exposed surface of the semiconductor layer. Additionally, the approach includes performing a low temperature anneal in an oxygen free environment followed by depositing a metal layer on the dopant layer. Furthermore, the approach includes alloying the metal layer with the dopant layer to form a semiconductor device junction where the semiconductor layer is composed of a Group III-V semiconductor material, the surface modification treatment occurs in a vacuum chamber to remove surface oxides from the exposed surface of the semiconductor layer, and each of the above processes occur at a low temperature.

A gate structure is formed straddling a first portion of a plurality of semiconductor fins that extend upwards from a topmost surface of an insulator layer. A dielectric spacer is formed on sidewalls of the gate structure and straddling a second portion of the plurality of semiconductor fins. Epitaxial semiconductor material portions that include a non-planar bottommost surface and a non-planar topmost surface are grown from at least the exposed sidewalls of each semiconductor fin not including the gate structure or the gate spacer to merge adjacent semiconductor fins. A gap is present beneath epitaxial semiconductor material portions and the topmost surface of the insulator layer. A second epitaxial semiconductor material is formed on the epitaxial semiconductor material portions and thereafter the second epitaxial semiconductor material is converted into a metal semiconductor alloy.

Low resistance and defect free epitaxial semiconductor material for providing merged FinFETs

A method for fabricating a semiconductor device includes receiving a gated finned substrate comprising an isolation layer with a semiconductor fin formed thereon and a gate formed over the semiconductor fin, depositing an atomic layer of dopant on a portion of the semiconductor fin that is laterally adjacent to the gate, forming a lateral spacer on a sidewall of the gate and above a gate extension portion of the atomic layer of dopant, and epitaxially growing a raised source or drain region on the semiconductor fin, that is laterally adjacent to the lateral spacer, from the atomic layer of dopant. The method may also include conducting a low temperature annealing process to diffuse the atomic layer of dopant to the raised source or drain region of the semiconductor fin. A corresponding apparatus is also disclosed herein.

3D atomic layer gate or junction extender

Growing community of inventors

Poughquag, NY, United States of America

Dae-Gyu Park