Samsung Electronics Co., Ltd.

Postech Academy-industry Foundation

Dae-Chul Jeong

Tae-Young Chung

Seong Joong Kim

Jae Sup Lee

Tae Young Chung

Jaesup Lee

Bum-Man Kim

Bum Man Kim

Han-Kyu Lee

A leakage current-based delay circuit is provided, wherein the delay circuit may include a first transistor circuit and a second transistor circuit, each transistor circuit may include a p-type transistor, an n-type transistor, an n-node between a drain node of the p-type transistor and a gate node of the n-type transistor, and a p-node between a gate node of the p-type transistor and a drain node of the n-type transistor. The p-node of the second transistor circuit may be charged based on a power source voltage through the first transistor circuit during a first time interval of an input signal, and the n-node of the second transistor circuit may be discharged based on a ground voltage through the first transistor circuit during the first time interval.

Leakage current-based delay circuit

A power circuit for reducing a leakage power using a negative voltage is provided. The power circuit includes a current source including a transistor including a gate. The power circuit further includes a current source control circuit connected to the gate of the transistor, and configured to apply a positive voltage to the gate of the transistor if the current source is to operate in an active mode, and apply the negative voltage to the gate of the transistor if the current source is to operate in an inactive mode.

Low power circuit for reducing leakage power using negative voltage

Growing community of inventors

Pohang-si, South Korea

Dae-Chul Jeong