Motorola Corporation

Dadario McCutcheon

David Michael Harrison

Kerry Lucille Johns-Vano

Phillip Anthony Carswell

Alison Ii

Kevin Thomas Campbell

A programmable cryptographic system (100) provides high performance cryptographic processing support for cryptographic algorithms. Two or more independent cryptographic algorithms may be performed at the same time through the processes of background staging and algorithm multi-tasking. A four stage software instruction pipeline and dynamically programmable function units support high performance cryptographic processing performance on the order of 60 mega bits per second (Mbps) aggregate throughput.

Cryptographic processing system with programmable function units and

Interface processor (IP)(50) sends and receives data units to and from an external host and a processor. The IP is capable of simultaneous, full duplex operation via high speed serial and parallel interfaces. The IP provides a highly flexible and configurable interface which is capable of interfacing to a variety of systems with minimal external hardware. The IP also provides a method of converting received data into data packets. The IP provides buffering of multiple data packets for use in systems having 'bursty' data traffic. The IP has a memory expansion capability allowing for changeable buffer capacities.

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Mesa, AZ, United States of America

Dadario McCutcheon