Hewlett Packard Enterprise Development LP

Hewlett-packard Development Company, L.p.

Dacheng Zhou

Daniel Alan Berkram

Ryan Barnhill

Zhubiao Zhu

Christopher Allan Poirier

Peter Tsugio Kurahashi

Jeffry D Yetter

Peter David Maroni

Michael James Marshall

Karl Joseph Bois

David W Quint

Christopher B Wilson

Clinton Harold Parker

Shad R Shepston

Clark Douglas Burnside

A TI-ADC circuit and method therefor include the use of first and second level clock generators configured to receive an asynchronous reference clock signal and generate a plurality of first and second clock signals, the second level clock generator including a plurality of clock dividers connected in series, respective ones of the plurality of clock dividers being configured to divide an input clock signal in accordance with a synchronization signal; a plurality of T/H circuits respectively configured to operate in accordance with one of the first clock signals; a plurality of sub-ADCs respectively configured to operate in accordance with one of the second clock signals, thereby to sample an input signal in a time-interleaved manner, wherein for a given clock divider of the plurality of clock dividers, the synchronization signal corresponds to an output clock of a clock divider immediately upstream from the given clock divider.

Clock synchronization in time-interleaved analog-to-digital conversion

A frontend circuit of a time-interleaved ADC is provided. The frontend circuit can include a track-and-hold circuit to sample an analog input signal to the ADC, a sub-ADC circuit to convert the sampled analog input signal to a digital output signal, and a source-follower circuit. An input of the source-follower circuit can be coupled to an output of the track-and-hold circuit, and an output of the source-follower circuit can be coupled to an input of the sub-ADC circuit. The source-follower circuit is to provide buffering between the track-and-hold circuit and the sub-ADC circuit. The circuit further includes a common-mode-adjusting circuit to dynamically adjust common-mode settings of the time-interleaved ADC. While adjusting the common-mode settings, the common-mode-adjusting circuit can adjust, separately, an input common-mode voltage of the track-and-hold circuit and an input common-mode voltage of the sub-ADC circuit based on current Process, Voltage, and Temperature (PVT) conditions.

Method and system for improving analog-to-digital conversion performance

Systems and methods are provided for a pipelined analog-to-digital converter (ADC) circuit. The pipelined ADC circuit comprises a plurality of stages. Each stage comprises a differential input configured to receive a differential signal, a multiplying digital-to-analog converter (MDAC) electrically coupled to the input configured to stack voltages of a set of capacitors; a comparator electrically disposed after the MDAC to compare the differential voltages; and a source follower buffer electrically coupled to the first signal line and the second signal line and electrically disposed after the comparator, wherein the MDAC is configured to amplify an output voltage using passive multiplication; and an alignment circuit communicatively connected to a digital bit output of each stage of the plurality of stages, wherein the alignment circuit is configured to delay a digital bit output of each stage for one or more clock cycles and output a digitized representation of a sampled differential signal.

Capacitor voltage stacking pipeline analog-to-digital converter (ADC)

Examples disclosed herein relate to set-reset (SR) latch circuits and methods for manufacturing the same. In some of the disclosed examples, a SR latch circuit includes an inverter storage loop for storing state information and a set of p-channel field-effect transistors (PFETs) for control circuitry. The PFETs may include first and second PFETs connected to a first node of the inverter storage loop, and third and fourth PFETs connected to a second node of the inverter storage loop. Gate terminals of the first and fourth PFETs may be connected to a first control input, and gate terminals of the second and third PFETs may be connected to a second control input.

Set-reset latches

One embodiment can provide a sampler for a decision feedback equalizer (DFE). The sampler can include a comparator comprising a resolver and a plurality of amplifiers coupled to the resolver. The plurality of amplifiers are to receive an input signal and one or more feedback signals, and the plurality of amplifiers are coupled to each other in parallel, thereby facilitating a summation of the input signal and the one or more feedback signals. The comparator is to generate an output based on the summation of the input signals and the one or more feedback signals. The sampler can further include an inverter to invert the output of the comparator. The inverted output of the inverter is sent to a tap-1 amplifier to generate a tap-1 feedback signal to be sent to the comparator at a next unit interval (UI).

Feedback circuit for a decision feedback equalizer

Apparatus, methods and systems to produce a protection voltage are disclosed. The apparatus includes circuitry to deliver a first supply voltage to a plurality of circuits, where the first supply voltage has a first magnitude, circuitry to deliver a second supply voltage to a part of the plurality of circuits, where the second supply voltage has a second magnitude, and circuitry to deliver a protection voltage to the part of the plurality of circuits when the second supply voltage is LOW and the first supply voltage is HIGH. The protection voltage has a magnitude that is a fraction of the magnitude of the first supply voltage. The apparatus includes circuitry that causes the delivery of the second supply voltage to the part of the plurality of circuits when the second supply voltage is turned HIGH subsequent to the second supply voltage being LOW when the first supply voltage is HIGH.

Methods and apparatus to generate a circuit protection voltage

A comparator includes a resolver controlled by a resolver clock signal and a differential amplifier controlled by a sampling clock signal. The resolver clock signal and the sampling clock signal are such that amplification at the differential amplifier during the reset phase of the resolver clock signal and the reset phase of the sampling clock signal begins during the resolving phase of the resolver.

Comparator

A technique includes determining a first phase delay associated with communication of a bit pattern having a first bit transition frequency over a communication channel; and determining a second phase delay associated with communication of a bit pattern having a second bit transition frequency greater than the first bit transition frequency over the communication channel. The technique includes regulating a compensation applied to a signal received from the communication channel based at least in part on a difference of the first and second phase delays.

Phase delay difference-based channel compensation

A differential amplifier includes a pair of cascode amplifiers. A voltage clamp is coupled to the pair of cascode amplifiers.

Differential amplifier

An example driver circuit includes a termination voltage circuit and a termination element coupled to the termination voltage circuit. The driver circuit also includes a current source switch coupled the termination element via a node. The driver circuit further includes a current source coupled to the current source switch. The current source switch and the termination voltage circuit are controlled via a control signal. The termination voltage circuit is to generate a termination voltage to match a node voltage of the node based on the control signal. The driver circuit further includes a load coupled to the termination element and the current source switch via the node. The driver circuit further includes a load voltage source coupled to the load. The node voltage is generated based on the load and the load voltage source.

Termination voltage circuits

In one example, a device may include a first push-pull driver with a first impedance and a push-pull driver unit with a second push-pull driver having a second impedance. The push-pull driver unit may be in parallel with the first push-pull driver. The device may further include a pulse generating unit to activate the push-pull driver unit for a delay time following an edge transition in an input signal. In one example, the device may have an output impedance that is less than the first impedance when the push-pull driver unit is activated.

Devices with push-pull drivers

In at least some examples, a communication device includes a photo-diode to convert an optical signal into an electrical current and an open-gain trans-impedance amplifier to amplify the electrical current. The communication device also includes a transmission line between the photo-diode and the open-gain trans-impedance amplifier. The open-gain trans-impedance amplifier includes a programmable input impedance that has been matched to an impedance of the transmission line.

Open-gain trans-impedance amplifier with programmable input impedance

Apparatuses and methods for an optical data interface with electrical forwarded clock are provided. One example optical data interface () can include a transmitter () having a data input () and a clock input (), and a receiver () having a data output () and a forwarded clock signal path (). An optical communication path () is coupled between the data input () and the data output () and configured to communicate a data signal. An electrical communication path () is coupled between the clock input () and the forwarded clock signal path (). The electrical communication path () is arranged to forward a clock signal used by the receiver () as a reference for the optical data signal.

Optical data interface with electrical forwarded clock

In at least some examples, a communication device includes a photo-diode to convert an optical signal into an electrical current and a feedback-based trans-impedance amplifier to amplify the electrical current. The communication device also includes a transmission line between the photo-diode and the feedback-based trans-impedance amplifier. The feedback-based trans-impedance amplifier includes a programmable input impedance that has been matched to an impedance of the transmission line.

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Fort Collins, CO, United States of America

Dacheng Zhou