Other

International Business Machines Corporation

Dac C Pham

Sebastian Theodore Ventrone

Steven Frederick Oakland

Robert Maurice Houle

Cang Ngoc Tran

Gary Stephen Ditlow

Mark D Sweet

Kenneth J Shaw

Jonathan Henry Raymond

Circuitry within a processor delays the launching of data onto an external bus by a factor that is proportional to the ratio of an internal processor clock speed to the system or external bus clock speed. This delay provides a delay in the launching of data to external bus devices so that these slower speed external bus devices have enough time to capture the data.

Apparatus for delaying the output of data onto a system bus

A digital clock signal multiplier circuit for generating an on-chip clock signal having a higher frequency than a system clock signal. A variable delay line, coupled to receive the system clock signal, is partitioned into (N) equal segments with each segment having multiple delay elements. Each of the delay elements is tapped to allow selective output of a corresponding delay signal. Multiple control switches, each associated with one of the delay elements, provide selective control for issuance of only one delay signal from each segment of the variable delay line. Delay signals selected for output are symmetrically offset and are fed to (N) pulse generators for the production of (N) pulse signals of duration substantially less than the period of the external clock signal. An output generator is coupled to receive the pulse signals output from the (N) pulse generators and produce therefrom the internal clock signal of desired frequency. Control circuitry selects the delay signals output from the (N) equal segments via appropriate activation of the associated control switches.

Digital clock signal multiplier circuit

A programmable logic array (PLA) is provided with a decoder at the input. Each product term line of the PLA has an associated power switch that is controlled by an output of the decoder. Only a portion of the PLA that includes the product term lines activated for a particular operation is powered up for that operation, thus minimizing power consumption.

Low power, high performance PLA

A control circuit and protocol are disclosed for an integrated circuit (such as a static PLA) wherein standby power is minimized during an idle processor state condition without loss of circuit outputs. For static PLAs, control circuits shutoff any active current path and drive the logic array outputs to zero whenever an idle state condition exists. Inputs to the logic array are held in static latches associated with the static PLA. The novel halt protocol includes: powering-down the logic macro upon initiation of an idle state by halting all internal clocks and then decoupling the logic array from power supply voltage VDD. Circuit power-up includes reactivating the logic array by first coupling the array to supply voltage VDD and allowing sufficient time for the outputs of the array and any associated logic to stabilize; and then restarting the previously halted internal clocks. Analogous techniques are also described for dynamic PLAs.

Growing community of inventors

Round Rock, TX, United States of America

Dac C Pham