Freescale Semiconductor,inc.

International Business Machines Corporation

Chartered Semiconductor Manufacturing Ltd (corporation)

Infineon Technologies North America Corp.

Da Zhang

Bich-Yen Nguyen

Voon-Yew Thean

Ted R White

Xiangdong Chen

Mariam G Sadaka

Brian A Winstead

Venkat Kolagunta

Jian Feng Chen

Srikanth Balaji Samavedam

Vishal P Trivedi

Young Way Teh

Laegu Kang

Alexander L Barr

Mohamed S Moosa

Melanie J Sherony

Victor H Vartanian

Weipeng Li

Veer Dhandapani

Ning Liu

Geng Wang

Haizhou Yin

Dae-Gyu Park

Kenneth Jay Stein

Jin-Ping Han

Yong Meng Lee

Paul Grudowski

Anda C Mocuta

Konstantin V Loiko

Terry Grant Sparks

Christopher C Hobbs

Christopher V Baiocco

Omar Zia

Jin Zheng Wallner

Vance H Adams

Brian J Goolsby

Veeraraghavan Dhandapani

Narayanan C Ramani

Yasuhito Shiho

Jill C Hildreth

Spencer E Williams

Xiangzheng Bo

Mark C Foisy

Darren V Goedeke

Jing Liu

Chendong Zhu

Jie Chen

Franck Arnaud

Paul A Grudowski

A first transistor and a second transistor are formed with different threshold voltages. A first gate is formed over the first region of a substrate for a first transistor and a second gate over the second region for a second transistor. The first region is masked. A threshold voltage of the second transistor is adjusted by implanting through the second gate while masking the first region. Current electrode regions are formed on opposing sides of the first gate and current electrode regions on opposing sides of the second gate.

Transistors with different threshold voltages

A transistor structure is formed by providing a semiconductor substrate and providing a gate above the semiconductor substrate. The gate is separated from the semiconductor substrate by a gate insulating layer. A source and a drain are provided adjacent the gate to define a transistor channel underlying the gate and separated from the gate by the gate insulating layer. A barrier layer is formed by applying nitrogen or carbon on opposing outer vertical sides of the transistor channel between the transistor channel and each of the source and the drain. In each of the nitrogen and the carbon embodiments, the vertical channel barrier retards diffusion of the source/drain dopant species into the transistor channel. There are methods for forming the transistor structure.

Transistor having gate dielectric protection and structure

A method and structure implant a first-type impurity within a substrate to form a channel region within the substrate adjacent a top surface of the substrate; form a gate stack on the top surface of the substrate above the channel region; and implant a second-type impurity within the substrate to form source and drain regions within the substrate adjacent the top surface. The channel region is positioned between the source and drain regions. The second-type impurity has an opposite polarity with respect to the first-type impurity. The method and structure implant a greater concentration of the first-type impurity, relative to a concentration of the first-type impurity within the channel region, to form a primary body doping region within the substrate below (relative to the top surface) the channel region; and to form secondary body doping regions within the substrate below (relative to the top surface) the source and drain regions.

Method and structure to improve body effect and junction capacitance

An integrated circuit structure includes a substrate and at least one pair of complementary transistors on or in the substrate. The pair of complementary transistors comprises a first transistor and a second transistor. The structure also includes a first stress-producing layer on the first transistor and the second transistor, and a second stress-producing layer on the first stress-producing layer over the first transistor and the second transistor. The first stress-producing layer applies tensile strain force on the first transistor and the second transistor. The second stress-producing layer applies compressive strain force on the first stress-producing layer, the first transistor, and the second transistor.

Balancing NFET and PFET performance using straining layers

A semiconductor fabrication process includes masking a first region, e.g., an NMOS region, of a semiconductor wafer, e.g., a biaxial, tensile strained silicon on insulator (SOI) wafer and creating recesses in source/drain regions of a second wafer region, e.g., a PMOS region. The wafer is then annealed in an ambient that promotes migration of silicon. The source/drain recesses are filled with source/drain structures, e.g., by epitaxial growth. The anneal ambient may include a hydrogen bearing species, e.g., Hor GeH, maintained at a temperature in the range of approximately 800 to 1000&#xb0; C. The second region may be silicon and the source/drain structures may be silicon germanium. Creating the recesses may include creating shallow recesses with a first etch process, performing an amorphizing implant to create an amorphous layer, performing an inert ambient anneal to recrystallize the amorphous layer, and deepening the shallow recesses with a second etch process.

Selective uniaxial stress modification for use with strained silicon on insulator integrated circuit

A semiconductor process and apparatus includes forming NMOS and PMOS transistors () with enhanced hole mobility in the channel region of a transistor by selectively relaxing part of a biaxial-tensile strained semiconductor layer () in a PMOS device area () to form a relaxed semiconductor layer (), and then epitaxially growing a bi-axially stressed silicon germanium channel region layer () prior to forming the NMOS and PMOS gate structures () overlying the channel regions, and then depositing a contact etch stop layer (-) over the NMOS and PMOS gate structures. Embedded silicon germanium source/drain regions () may also be formed adjacent to the PMOS gate structure () to provide an additional uni-axial stress to the bi-axially stressed channel region.

CMOS process with optimized PMOS and NMOS transistor devices

Method for forming a transistor having gate dielectric protection and structure

A semiconductor process and apparatus includes forming &#x3c;100&#x3e; channel orientation CMOS transistors () with enhanced hole mobility in the NMOS channel region and reduced channel defectivity in the PMOS region by depositing a first tensile etch stop layer () over the PMOS and NMOS gate structures, etching the tensile etch stop layer () to form tensile sidewall spacers () on the exposed gate sidewalls, and then depositing a second hydrogen rich compressive or neutral etch stop layer () over the NMOS and PMOS gate structures () and the tensile sidewall spacers (). In other embodiments, a first hydrogen-rich etch stop layer () is deposited and etched to form sidewall spacers () on the exposed gate sidewalls, and then a second tensile etch stop layer () is deposited over the NMOS and PMOS gate structures () and the sidewall spacers ().

Method for transistor fabrication with optimized performance

A semiconductor process and apparatus fabricate a metal gate electrode () and an integrated semiconductor resistor () by forming a metal-based layer () and semiconductor layer () over a gate dielectric layer () and then selectively implanting the resistor semiconductor layer () in a resistor area () to create a conductive upper region () and a conduction barrier (), thereby confining current flow in the resistor semiconductor layer () to only the top region () in the finally formed device.

Semiconductor resistor formed in metal gate stack

A stress memorization technique (SMT) film is deposited over a semiconductor device. The SMT film is annealed with a low thermal budget anneal that is sufficient to create and transfer the stress of the SMT film to the semiconductor device. The SMT film is then removed. After the SMT film is removed, a second anneal is applied to the semiconductor device sufficiently long and at a sufficiently high temperature to activate dopants implanted for forming device source/drains. The result of this approach is that there is minimal gate dielectric growth in the channel along the border of the channel.

Method of forming a semiconductor device using stress memorization

A method for forming a semiconductor device is provided. The method includes forming a semiconductor layer. The method further includes forming a gate structure overlying the semiconductor layer. The method further includes forming a high-k sidewall spacer adjacent to the gate structure. The method further includes forming a recess in the semiconductor layer, the recess aligned to the high-k sidewall spacer. The method further includes forming an in-situ doped epitaxial material in the recess, the epitaxial material having a natural lattice constant different from a lattice constant of the semiconductor layer to create stress in a channel region of the semiconductor device.

Source/drain stressors formed using in-situ epitaxial growth

An electronic device can include a semiconductor fin overlying an insulating layer. The electronic device can also include a semiconductor layer overlying the semiconductor fin. The semiconductor layer can have a first portion and a second portion that are spaced-apart from each other. In one aspect, the electronic device can include a conductive member that lies between and spaced-apart from the first and second portions of the semiconductor layer. The electronic device can also include a metal-semiconductor layer overlying the semiconductor layer. In another aspect, the semiconductor layer can abut the semiconductor fin and include a dopant. In a further aspect, a process of forming the electronic device can include reacting a metal-containing layer and a semiconductor layer to form a metal-semiconductor layer. In another aspect, a process can include forming a semiconductor layer, including a dopant, abutting a wall surface of a semiconductor fin.

Electronic device including a semiconductor fin

A semiconductor device structure is made on a semiconductor substrate having a semiconductor layer having isolation regions. A first gate structure is formed over a first region of the semiconductor layer, and a second gate structure is over a second region of the semiconductor layer. A first insulating layer is formed over the first and second regions. The first insulating layer can function as a mask during an etch of the semiconductor layer and can be removed selective to the isolation regions and the sidewall spacers. The first insulating layer is removed from over the first region to leave a remaining portion of the first insulating layer over the second region. The semiconductor layer is recessed in the first region adjacent to the first gate to form recesses. A semiconductor material is epitaxially grown in the recesses. The remaining portion of the first insulating layer is removed.

Forming a semiconductor device having epitaxially grown source and drain regions

A semiconductor process and apparatus includes forming PMOS transistors () with enhanced hole mobility in the channel region by forming a hydrogen-rich silicon nitride layer () on or adjacent to sidewalls of the PMOS gate structure as either a hydrogen-rich implant sidewall spacer () or as a post-silicide hydrogen-rich implant sidewall spacer (), where the hydrogen-rich dielectric layer acts as a hydrogen source for passivating channel surface defectivity under the PMOS gate structure.

Method for PFET enhancement

A method for forming a semiconductor device includes providing a substrate and forming a p-channel device and an n-channel device, each of the p-channel device and the n-channel device comprising a source, a drain, and a gate, the p-channel device having a first sidewall spacer and the n-channel device having a second sidewall spacer. The method further includes forming a liner and forming a tensile stressor layer over the liner and removing a portion of the tensile stressor layer from a region overlying the p-channel device. The method further includes transferring a stress characteristic of an overlying portion of a remaining portion of the tensile stressor layer to a channel of the n-channel device. The method further includes using the remaining portion of the tensile stressor layer as a hard mask, forming a first recess and a second recess adjacent the gate of the p-channel device.

Method of making a semiconductor device using a stressor

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Austin, TX, United States of America

Da Zhang