United Microelectronics Corp.

Da-Wen Hsia

Kuo-Chi Lin

Terry Chung-Yi Chen

Cheng-Chih Kung

Cheng-Chieh Huang

Cheng-Chiech Huang

A method for preventing the cluster defect of HSG is disclosed. Where the cluster defect means that when wafer with HSGs are cleaned just when HSGs are formed, there are a plurality of clusters appear on HSGs. In comparison with conventional fabrication that wafer and HSGs are directly cleaned just when these HSGs are formed. The idea behind the invention is that when HSGs are formed, a heat treatment is applied to change surface states of HSGs before wafer and HSGs are cleaned. Owing to the fact that these surface states of HSGs are improved by the heat treatment, no cluster will be formed during following clean process. Thus, the formation of cluster is obviously protected and then quality of any application of HSGs is improved by the invention.

Method for preventing the cluster defect of HSG

A method for forming a capacitor containing selective hemispherical grained (S-HSG) polysilicon is disclosed. In this invention, dopant implantation is incorporated after the S-HSG growth to replace conventional wet clean procedure. The elimination of the cleaning treatments avoids the incidents of residue particles (due to cleaning) and minimizes numerous structure defects. The incorporation of the ion implantation technique would make up the insufficiency of doping requirement by applying in-diffusion alone. The combination of the in-diffusion and the implantation for doping procedure could maintain the device with good capacitance level even though the pre-clean procedure is excluded.

Method for forming a capacitor having selective hemispherical grained polysilicon

A method for ensuring no capacitor peeling at the edge of a wafer in the fabrication of dynamic random access memory (DRAM) is disclosed. The method includes first providing a semiconductor substrate having a semiconductor structure formed thereon. A dielectric layer is then formed overlying the semiconductor structure, and patterned for defining a contact window. Followed by, the deposition of a silicon layer over the dielectric layer that fills up the contact window. Consequentially, a photoresist layer is coated overlying the silicon layer, where it will be rinsed twice by a combination of an online EBR (and/or a WEE) and an offline EBR at a distance inwardly away from the edge of the wafer in process for removing a portion of the photoresist to avoid abnormal capacitor formation in later stages. Then, a photolithography process is carried out against the photoresist layer to form a photoresist mask. Finally, the silicon layer is etched where it is not covered by the photoresist mask to form a lower capacitor electrode. The photoresist mask is stripped as to conclude the present invention.

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Da-Wen Hsia