Globalfoundries Singapore Pte. Ltd.

Da-Wei Lai

Mahadeva Iyer Natarajan

Ying-Chang Lin

Handoko Linewih

Manjunatha Govinda Prabhu

Ming Li

Ryan Shan

Purakh Raj Verma

Jeoung Mo Koo

Shan Ryan

Yi Shan

An improved nLDMOS ESD protection device having an increased holding voltage is disclosed. Embodiments include: providing in a substrate a DVNW region; providing a HVPW region in the DVNW region; providing bulk and source regions in the HVPW region; providing a drain region in the DVNW region, separate from the HVPW region; and providing a polysilicon gate over a portion of the HVPW region and the DVNW region.

Latch-up immunity nLDMOS

An ESD module includes an ESD circuit coupled between a first source and a second source. A trigger circuit is also included in the ESD module for activating the ESD circuit to provide a low resistance current path between the first and second sources. The trigger circuit includes a reverse diode between the first source and the ESD circuit or between the second source and main ESD circuit. The trigger circuit provides a low trigger voltage to activate the ESD circuit.

ESD protection for high voltage applications

A device having a substrate defined with a device region is presented. The device region includes an ESD protection circuit having a transistor. The transistor includes a gate having first and second sides, a first diffusion region disposed adjacent to the first side of the gate and a second diffusion region displaced away from the second side of the gate. The device includes a first device well encompasses the device region and a second device well disposed within the first device well. The second device well encompasses the first diffusion region and at least a part of the gate. The device also includes a third well which is disposed within the second device well and a drain well which encompasses the second diffusion region and extends below the gate.

ESD protection circuit

A device is presented. The device includes a first circuit coupled to first and second power rails of the device. The first circuit is subject to a latch up event in the presence of a latch up condition. The latch up event includes a low resistance path created between the first and second power rails. The device also includes a latch up sensing (LUS) circuit coupled to the first circuit. The LUS circuit is configured to receive a LUS input signal from the first circuit and generates a LUS output signal to the first circuit. When the input signal is an active latch up signal which indicates the presence of a latch up condition, the LUS circuit generates an active LUS output signal which creates a break in the low resistance path to terminate the latch up event.

Latch up detection

An approach for providing a latch-up robust silicon control rectifier (SCR) is disclosed. Embodiments include providing a first N+ region and a first P+ region in a substrate for a SCR; providing first and second n-well regions in the substrate proximate the first N+ and P+ regions; providing a second N+ region in the first n-well region, and a second P+ region in the second n-well region; and coupling the first N+ and P+ regions to a ground rail, the second N+ region to a power rail, and the second P+ region to an I/O pad.

Latch-up robust SCR-based devices

An acceptable voltage margin between a voltage level for triggering electrostatic current discharge and a voltage level for programming operation of an OTP device is determined. Activation of an ESD protection circuit is controlled in part in response to a false trigger prevention circuit. To avoid gate oxide breakdown that may occur with a MOSFET protection device used for higher voltage requirements of an OTP device, the ESD protection circuit employs a bipolar transistor.

False-triggered immunity and reliability-free ESD protection device

Protecting a gate dielectric is achieved with a gate dielectric protection circuit coupled to a transistor at risk. The protection circuit is activated to reduce the voltage across the gate dielectric (V) to below its breakdown voltage (V). The protection circuit is activated when an ESD event is detected. The protection circuit provides a protection or ESD bias to reduce Vbelow V.

Gate dielectric protection

An ESD circuit is disclosed. The ESD circuit includes a pad and a ground and a sensing element coupled between the pad and ground for sensing an ESD current. The sensing element generates an active sense output signal when an ESD current is sensed and an inactive sense output signal when no ESD current is sensed. The ESD circuit also includes a bypass element comprising a bi-polar junction transistor. The bypass element is coupled in parallel to the sensing element between the pad and ground. The active sense output signal causes the bypass element to be activated to provide a current path between the pad and ground.

An RC-based electrostatic discharge protection device provides an extended snapback trigger voltage range, thereby avoiding latch-up. Two parallel current discharge paths are provided between supply terminals during an electrostatic discharge event by virtue of an added external resistor. The first current discharge path includes body resistance of the protection device and the second current discharge path includes the external resistor.

Latch-up free RC-based NMOS ESD power clamp in HV use

An ESD module is presented. The ESD module includes an ESD circuit and a latch-up (LU) control circuit. The ESD circuit has a pad terminal and a low power source terminal. The LU control circuit includes a first LU terminal coupled to a high power source and an LU output terminal coupled to the ESD circuit. The ESD module has first and second operating modes. In the first operating mode, the LU control circuit is deactivated and the ESD circuit has a first triggering current Iwhich is less than 100 mA. In the second operating mode, the LU control circuit is activated and the ESD circuit has a second triggering current Iwhich is greater than 100 mA.

Latch-up immune ESD protection

A clamp circuit includes both nmos and pmos devices connected in series between a voltage source terminal, such as an integrated circuit pad, and ground. A trigger unit, connected between the voltage source and ground, includes a plurality of output terminals coupled to the clamp circuit. The trigger unit is responsive to a voltage threshold, such as caused by an ESD occurrence, between the voltage source and ground to apply clamping signals at its output terminals to couple the voltage source terminal to ground through both nmos and pmos devices.

Power clamp for high voltage integrated circuits

A triple stack NMOS integrated circuit structure protection circuit for a plurality of terminals operative at respective voltage levels is coupled between the plurality of terminals. First and second NMOS elements of the triple stack NMOS share a common active region. A third NMOS element, vertically positioned with respect to the first and second NMOS elements, has an active region separate from the active region of the first and second NMOS elements. The first, second and third NMOS elements are connected in series between two terminals of the plurality of terminals.

High noise immunity with latch-up free ESD clamp

A device having a substrate defined with a device region is presented. The device region includes an ESD protection circuit having a transistor. The transistor includes a gate having first and second sides, a first diffusion region adjacent to the first side of the gate and a second diffusion region displaced away from the second side of the gate. The device includes a first device well which encompasses the device region and a second device well disposed within the first device well. The device further includes a drift well which encompasses the second diffusion region of which edges of the drift well do not extend below the gate and is away from a channel region, and a drain well which is disposed under the second diffusion region and extends below the gate.

A device having an ESD module is disclosed. The ESD module includes an ESD circuit coupled between first and second rails and a control circuit coupled between the rails and to the ESD circuit. When the control circuit senses an ESD event, it causes the ESD circuit to create a current path between the rails to dissipate ESD current. When no ESD event is sensed, the control circuit ensures that no current path is created between the rails to prevent latch-up.

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Singapore, Singapore

Da-Wei Lai