Chartered Semiconductor Manufacturing Ltd (corporation)

Da Jin

Yong Meng Lee

David Vigar

A method of forming a double-gated transistor having a rounded active region to improve GOI and leakage current control comprises the following steps, inter alia. An SOI substrate is patterned and a rounded oxide layer is formed over the exposed side walls of a patterned upper SOI silicon layer. A dummy layer, having an opening defining a gate, is formed over the exposed patterned top oxide layer and the exposed portions of the upper SOI silicon layer. An undercut is formed into the undercut lower SOI oxide layer and the exposed gate area portion of the oxide layer is removed. The portion of the rounded oxide layer within the gate area is removed and a conformal oxide layer is formed over a part of the structure. A gate is formed within the second patterned dummy layer opening and the patterned dummy layer is removed to form the double gated transistor.

Double-gated silicon-on-insulator (SOI) transistors with corner rounding

Method of forming double-gated silicon-on-insulator (SOI) transistors with corner rounding

A method of forming a double-gated transistor comprising the following sequential steps. A substrate having an SOI structure formed thereover is provided. The SOI structure including a lower SOI oxide layer and an upper SOI silicon layer. The SOI silicon layer is patterned to form a patterned SOI silicon layer including a source region and a drain region connected by a channel portion. An encasing oxide layer is formed over the patterned SOI silicon layer to form an encased patterned SOI silicon layer. A patterned dummy layer is formed over the encased patterned SOI silicon layer. The patterned dummy layer having an opening, with exposed side walls, exposing: the channel portion of the encased patterned SOI silicon layer; and portions of the upper surface of the SOI oxide layer. Offset spacers are over the exposed side walls of the patterned dummy layer opening. The SOI oxide layer is etched while minimizing the undercut portions of the upper surface of the SOI oxide layer are undercut into the SOI oxide layer to form a minimal undercut. The minimizing undercutting process also removing the offset spacers and the encasing oxide layer over the channel portion of the patterned SOI silicon layer. A conformal oxide layer is formed around the channel portion of the patterned SOI silicon layer. A gate is formed within the patterned dummy layer opening. The gate including an upper gate above the patterned SOI silicon layer and a lower gate under the patterned SOI silicon layer. The patterned dummy layer is then removed to form the double-gated transistor.

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Shanghai, China

Da Jin