Samsung Electronics Co., Ltd.

Samsung Electro-mechanics Co., Ltd.

Da Hee Kim

Young Gwan Ko

Byung Ho Kim

Joo Young Choi

Sung Won Jeong

Joon Sung Kim

Tae Wook Kim

Young Min Kim

Jae Hoon Choi

Doo Hwan Lee

Hee Sook Park

Sung Hyo Jeong

A fan-out semiconductor package includes: a first connection member having a through-hole; a semiconductor chip disposed in the through-hole of the first connection member and having an active surface having connection pads disposed thereon and an inactive surface opposing the active surface; an encapsulant encapsulating at least portions of the first connection member and the inactive surface of the semiconductor chip; a second connection member disposed on the first connection member and the active surface of the semiconductor chip; and a heat dissipation layer embedded in the encapsulant so that one surface thereof is exposed. The first connection member and the second connection member include, respectively, redistribution layers electrically connected to the connection pads of the semiconductor chip.

Fan-out semiconductor package

A semiconductor package includes a connection member having a first surface and a second surface opposing each other and including a first redistribution layer on the second surface and at least one second redistribution layer on a level different from a level of the first redistribution layer; a semiconductor chip on the first surface of the connection member; a passivation layer on the second surface of the connection member, and including openings; UBM layers connected to the first redistribution layer through the openings; and electrical connection structures on UBM layers. An interface between the passivation layer and the UBM layers has a first unevenness surface, an interface between the passivation layer and the first redistribution layer has a second unevenness surface, connected to the first unevenness surface, and the second unevenness surface has a surface roughness greater than a surface roughness of the second redistribution layer.

Semiconductor package

A fan-out semiconductor package includes: a first connection member having a through-hole; a semiconductor chip disposed in the through-hole and having an active surface having connection pads disposed thereon and an inactive surface opposing the active surface; an encapsulant encapsulating at least portions of the first connection member and the inactive surface of the semiconductor chip; a second connection member disposed on the first connection member and the active surface of the semiconductor chip; a resin layer disposed on the encapsulant; and a rear redistribution layer embedded in the encapsulant so that one surface thereof is exposed by the encapsulant, wherein the resin layer covers at least portions of the exposed one surface of the rear redistribution layer, and the rear redistribution layer is electrically connected to the redistribution layer of the first connection member through connection members formed in first openings penetrating through the resin layer and the encapsulant.

A semiconductor package includes a semiconductor chip having a first surface on which connection pads are disposed and a second surface opposing the first surface; a connection member including a first insulating layer disposed on the first surface of the semiconductor chip, a wiring pattern disposed on the first insulating layer and having a top surface of which an edge is rounded, a via penetrating through the first insulating layer and electrically connecting the connection pads to the wiring pattern, and a second insulating layer disposed on the first insulating layer and covering the wiring pattern; and an encapsulant disposed on the connection member and encapsulating the semiconductor chip.

A semiconductor package includes a support member having first and second surfaces, having a cavity, and including a wiring structure, a semiconductor chip having connection pads, a connection member including a first insulating layer, a first redistribution layer on the first insulating layer, and a plurality of first vias connecting the wiring structure and the connection pads to the first redistribution layer and an encapsulant encapsulating the semiconductor chip, The wiring structure includes wiring patterns disposed on the second surface of the support member, and the first insulating layer includes a first insulating coating covering the wiring patterns and a second insulating coating disposed on the first insulating coating and having a higher level of flatness than that of the first insulating coating.

Semiconductor package with improved flatness of an insulating layer formed on patterns

A fan-out semiconductor package includes: a core member including a support layer, a first wiring layer, a second wiring layer, and through-vias and having a through-hole; a semiconductor chip disposed in the through-hole; an encapsulant covering the core member and the semiconductor chip and filling at least portions of the through-hole; a connection member including an insulating layer disposed on the first wiring layer and the semiconductor chip, a redistribution layer disposed on the insulating layer, first vias electrically connecting the redistribution layer and the connection pads to each other, and second vias electrically connecting the redistribution layer and the first wiring layer to each other; and a passivation layer disposed on the insulating layer and covering the redistribution layer, wherein a thickness of the passivation layer is within half a distance from an inactive surface of the semiconductor chip to a lower surface of the encapsulant.

A fan-out semiconductor package includes: a semiconductor chip; a first connection member including a plurality of redistribution layers and one or more layer of vias; an encapsulant; and a second connection member, wherein the encapsulant has first openings exposing at least portions of the first connection member, the first connection member has second openings exposing at least portions of a redistribution layer disposed at an uppermost portion among the plurality of redistribution layers, at least portions of the first openings and the second openings overlap each other, and a content of a metal constituting the plurality of redistribution layers and the one or more layer of vias is higher in a lower portion of the first connection member than in an upper portion of the first connection member.

Growing community of inventors

Suwon-si, South Korea

Da Hee Kim