Taiwan Semiconductor Manufacturing Comp. Ltd.

Da-Ching Chiou

Yu-Chao Lin

Yu-Sheng Chen

Carlos H Diaz

Tung-Ying Lee

Jau-Yi Wu

A memory cell includes a dielectric structure, a storage element structure, and a top electrode. The storage element structure is disposed in the dielectric structure, and the storage element structure includes a first portion and a second portion. The first portion includes a first side and a second side opposite to the first side, where a width of the first side is less than a width of the second side. The second portion is connected to the second side of the first portion, where a width of the second portion is greater than the width of the first side. The top electrode is disposed on the storage element structure, where the second portion is disposed between the first portion and the top electrode.

Memory cell, semiconductor device having the same, and methods of manufacturing the same

A memory cell includes a bottom electrode, a first dielectric layer, a top electrode, and a variable resistance layer. The first dielectric layer laterally surrounds the bottom electrode. The top electrode is disposed over the bottom electrode and the first dielectric layer. The variable resistance layer is sandwiched between the bottom electrode and the top electrode and between the first dielectric layer and the top electrode. The variable resistance layer exhibits a T-shape in a cross-sectional view.

Memory cell, integrated circuit, and manufacturing method of memory cell

A memory cell includes a bottom electrode, a storage element layer, a first buffer layer, and a top electrode. The storage element layer is disposed over the bottom electrode. The first buffer layer is interposed between the storage element layer and the bottom electrode, where a thermal conductivity of the first buffer layer is less than a thermal conductivity of the storage element layer. The top electrode is disposed over the storage element layer, where the storage element layer is disposed between the top electrode and the first buffer layer.

A memory cell includes a bottom electrode, a first dielectric layer, a variable resistance layer, and a top electrode. The first dielectric layer laterally surrounds the bottom electrode. A top surface of the bottom electrode is located at a level height lower than that of a top surface of the first dielectric layer. The variable resistance layer is disposed on the bottom electrode and the first dielectric layer. The variable resistance layer contacts the top surface of the bottom electrode and the top surface of the first dielectric layer. The top electrode is disposed on the variable resistance layer.

A memory device includes a conductive wire, a first 2-D material layer, a phase change element, and a top electrode. The first 2-D material layer is over the conductive wire. The phase change element extends along a surface of the first 2-D material layer distal to the conductive layer. The top electrode is over the phase change element.

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Hsinchu, Taiwan

Da-Ching Chiou