Chengdu Monolithic Power Systems Co., Ltd.

Monolithic Power Systems, Inc.

Da Chen

Zhengwei Zhang

Eric Braun

Kaiwei Yao

Tianzhu Zhang

Wei Mao

Yue Leng

A multi-time programmable memory cell has a differential multi-time programmable memory cell and a second-level latch cell. The differential multi-time programmable memory cell provides a first balance signal and a second balance signal, and the second-level latch cell receives the first balance signal and the second balance signal and provides an output signal according to the first balance signal and the second balance signal based on a first latch control signal and a second latch control signal.

Multi-time programmable non-volatile memory cell and associated circuits

A voltage control circuit for a memory cell having a floating gate transistor and a capacitive device, comprising a first input terminal, a second input terminal, a first output terminal and a second input terminal, wherein the first input terminal is configured to receive a power supply voltage, the second input terminal is configured to receive a ground reference, and wherein based on the power supply voltage and the ground reference, the first output terminal and the second output terminal respectively provides a first voltage signal and a second voltage signal, and wherein a voltage value of the first voltage signal is twice the power supply voltage, and a maximum of a voltage difference between the first voltage signal and the second voltage signal is three times the power supply voltage.

Voltage control circuit for memory cell and the method thereof

A charger system with a digital interface circuit, wherein the digital interface circuit has an N-bit control register, wherein N is a positive integer no less than 2, and wherein the N-bit register has a primary state machine, at a first portion of addresses of the control register, configured to instruct operation statuses of a system management bus host; and a secondary state machine, at a second portion of addresses of the control register, configured to instruct a data bit of transmission of a corresponding control instruction under each of the operation statuses of the system management bus host.

Charger system, digital interface circuit and associated control method

An OTP memory cell and an OTP memory circuit. The OTP memory cell having a memory module, a write module, a read module, and a load module. Data may be written into the memory module once the write module is active; and data may be read out of the memory module once the read module is active. The OTP memory cell may also have a first latch module and a second latch module.

One-time programmable memory cell and circuit

A phase-shift dimming circuit for LED controller having a delay signal generator configured to receive a PWM input signal, and to provide a plurality of pairs of set signal and reset signal, the set signal and the reset signal respectively having pulses; and a plurality of latches configured to respectively receive the plurality of pairs of set signal and reset signal to generate a plurality of PMW output signals, each of the PWM output signals having pulses, and wherein the rising edge of the pulses of the PWM output signals is based on the corresponding set signal pulses, and the falling edge of the pulses of the PWM output signals is based on the corresponding reset signal pulses.

Phase-shift dimming for LED controller and the method thereof

The present invention discloses an analog switching circuit having a first terminal receiving an input signal, a second terminal providing an output signal and a control terminal receiving a switching control signal. The analog switching circuit has a first logic circuit providing a first control signal and a second control signal based on the switching control signal; an NMOS and a PMOS coupled between the first terminal and the second terminal, and controlled by the first control signal and the second control signal respectively; a first control circuit controls the backgate voltage of the NMOS based on the input signal and the switching control signal; and a second control circuit controls the backgate voltage of the PMOS based on the input signal and the switching control signal.

Growing community of inventors

Chengdu, China

Da Chen