Lsi Logic Corporation

D Tony Stelliga

Michael D Rostoker

John P Daane

Sanjay M Desai

Willem A Engelse

Dave Paolino

Paul Bergantino

A digital network system accommodates a plurality of network protocols. The digital network system includes a backbone bus for communicating digital information. A first switching interface unit is coupled to the backbone bus and has at least one port connected to a first network. A second switching interface unit is also coupled to the backbone bus and has at least one port connected to a second network. The first and second interface units transferring digital information in first and second network protocols, respectively. First and second memories are coupled to the backbone bus and to the first and second switching interface units, respectively, and store digital information to be transferred between the switching interface units via the backbone bus. The first switching interface unit and the first memory are formed on a single substrate, and the second switching interface unit and the second memory are formed on a single substrate. A controller is coupled to the backbone bus and controls the transfer of digital information from the first switching interface unit to the second switching interface unit.

Network architecture

A single chip network interface apparatus includes a host interface circuit for communication with a host system bus, a network interface circuit for interfacing with a network bus, a dual port RAM coupled to the host interface circuit and also coupled to the network interface circuit, and a processor coupled to the dual port ram for converting packets of information between network protocol format and a format suitable for the host system bus.

High speed network interface having SAR plus physical interface

An adaptive error detection and correction apparatus for an Asynchronous Transfer Mode (ATM) network device comprises a sensing unit for sensing a congestion condition in the ATM network and a global pacing rate unit for adaptively reducing a maximum allowable transmission ratio of ATM cells containing information to idle ATM cells in response to a sensed congestion condition. A processor stores a number corresponding to a relatively high maximum allowable transmission ratio in the global pacing rate register in the absence of a sensed congestion condition, and stores a number corresponding to a relatively low maximum allowable transmission ratio in the global pacing rate register in response to a sensed congestion condition. A controller adjusts the maximum allowable transmission ratio in accordance with the number stored in the global pacing rate register. A plurality of peak pacing rate counters reset to predetermined values upon decrementation to zero, the predetermined values corresponding to service intervals for segmentation of Conversion Sublayer Payload Data Unit (CD-PDU)s. The processor further includes circuitry for assigning the counters to selected CD-PDUs, and sensing the counters to determine whether or not segmentation of the selected CD-PDUs is within the respective service intervals. The apparatus further includes a channel group credit register having bits corresponding to the respective counters.

Error detection and correction apparatus for an asynchronous transfer

A network adapter formed on a single semiconductor substrate. The network adapter includes a host bus interface circuit adapted to be connected to a host data bus. A buffer memory is connected to the host bus interface circuit and temporarily stores digital information received from the host data bus. The digital information received from the host data bus are reformatted into packets according to a network protocol by a reformatting circuits. A processor and a network interface circuit are connected to the reformatting circuits. The processor controls the reformatting of the digital information. The network interface circuit is adapted to be connected to a digital network employing the network protocol.

Switched network hub on a chip

A single chip network adapter apparatus has each component disposed on a single semiconductor chip. The network adapter includes a host interface circuit which is adapted for connection directly to a host system bus. The host interface circuit sends information to and receives information form the host system bus, and has random access memory coupled thereto. A processor is coupled to the random access memory and formats information received from the host system bus to a network protocol format. The processor also converts information received in a network protocol format to a form suitable for the host system bus. A network interface circuit is coupled to the random access memory and is adapted for connection directly to a network. The network interface circuit sends information formatted by the processor to the network and receives information to be converted by the processor from the network.

Single chip network adapter apparatus

A remote connection digital processing device with network capability includes on a single chip asynchronous transfer mode (ATM) network protocol processing system interconnection circuits and Motion Picture Experts Group (MPEG) decoder circuits. The ATM interconnection circuits include a physical-layer medium dependent (PMD) unit connected to an ATM network. A transmission convergence (TC)/Framer unit is connected to the PMD unit. An ATM segmentation and reassembly (SAR) unit is connected to the PMD unit. Packet conversion logic is coupled to the ATM SAR unit for converting ATM packets to MPEG format. The MPEG decompression decoder circuits include a demodulator decryption unit coupled to the packet conversion logic. A video decoder is coupled to the demodulator decryption unit. An audio decoder is coupled to the demodulator decryption circuit. A display is coupled to the video decoder. Audio output devices are coupled to the audio decoder.

High speed single chip digital video network apparatus

The port in a packet network switching system that a packet should be associated with is determined by retrieving packet address information for a packet that is to be transmitted. A predetermined number of bits from the packet address information is selected to use a hash key, which is used to compute a table address. The contents of the table at that address are compared with the packet address information. If it matches, the packet is transmitted over the port associated with that particular destination address. If it does not match, the table address is incremented by one, and the contents of the new table location identified by the incremented address are compared with the packet address information. A high speed digital video network apparatus which utilizes the hashing function is implemented on a single integrated circuit chip, and includes a network protocol processing system interconnection, compression/decompression circuits, and encoder/decoder circuits.

Multi-port network adapter

A high speed digital video network apparatus is implemented on a single integrated circuit chip, and includes a network protocol processing system interconnection, compression/decompression circuits, and encoder/decoder circuits. The interconnection includes a packet conversion logic which converts between a network protocol, such as Asynchronous Transfer Mode (ATM) packets, and the data protocol used to handle large data streams, such as Motion Picture Experts Group (MPEG) packets. The interconnection further includes a Virtual Channel Memory (VCM) for storing ATM cells for segmentation and reassembly, a Direct Memory Access (DMA) controller for connecting the VCR to the compression/decompression circuits, a Parallel Cell Interface (PCI) for connecting the VCM to an ATM network, a Pacing Rate Unit (PCU) for automatically reducing the maximum transmission rate in response to a sensed congestion condition in the network, and a Reduced Instruction Set Computer (RISC) microprocessor for controlling the DMA controller and transfers between the memory, a host and the ATM network, for performing segmentation and reassembly of Conversion Sublayer Payload Data Units (CD-PDUs), and for performing conversion between the ATM Protocol and the MPEG protocol. The compression/decompression and decoder/encoder circuits may utilize MPEG to compress digitized images and motion video into compact data streams that can be moved across networks with bandwidths too narrow to accommodate the uncompressed data. The operating program for the RISC microprocessor is stored in a volatile Instruction Random Access Memory (IRAM) in the form of firmware which can be downloaded at initialization.

A random number generating apparatus for an interface unit of a Carrier Sense with Multiple Access and Collision Detect (CSMA/CD) Ethernet data network. The interface unit includes a transmit backoff unit for implementing a backoff algorithm in response to a network collision signal and a random number. The apparatus comprises a dual mode random number generator and a multiplexer for switching the random number generator between modes in accordance with the serial address bits of a data packet being processed by the interface unit. The random number generator includes a 25 stage linear feedback shift register. The multiplexer has two signal inputs connected to outputs of the 18th and 22nd stages of the shift register respectively, a switch input connected to receive the serial address bits and an output connected in circuit to an input of the shift register.

Random number generating apparatus for an interface unit of a carrier

An asynchronous transfer mode (ATM) processing system interconnection or termination unit is implemented on a single integrated circuit chip. The unit includes a universal protocol device having Virtual Channel Memory (VCR) for storing ATM cells for segmentation and reassembly, a Direct Memory Access (DMA) controller for interconnecting the VCR to a host unit, and a Parallel Cell Interface (PCI) for interconnecting the VCR to an ATM network. A Reduced Instruction Set Computer (RISC) microprocessor controls the DMA controller as well as segmentation and reassembly of Conversion Sublayer Payload Data Unit (CS-PDU)s and transfer between the memory, the host and the ATM network and other operations of the device using single clock cycle instructions. The operating program for the RISC microprocessor is stored in a volatile Instruction Random Access Memory (IRAM) in the form of firmware which is downloaded at initialization. The program can be user designed to accommodate changes in ATM network protocols and congestion handling routines. A Pacing Rate Unit (PRU) includes a global pacing rate register which automatically reduces the maximum transmission rate of ATM cells in response to a sensed congestion condition in the ATM network.

Single chip universal protocol multi-function ATM network interface

A single chip hub for an electronic communication network comprises a packet memory for storing data packets, a Reduced Instruction Set Computer (RISC) processor for processing the packets, and a plurality of media access interfaces. A Direct Memory Access (DMA) controller transfers packets transferring packets between the packet memory and the interfaces. A packet attribute memory stores attributes of the data packets, and an attribute processor performs a non-linear hashing algorithm on an address of a packet being processed for accessing a corresponding attribute of said packet in the packet attribute memory. An address window filter identifies the address of a packet being processed by examining only a predetermined portion of said address, and can comprise a dynamic window filter or a static window filter.

Single chip network hub with dynamic window filter

Error detection and correction method for an asynchronous transfer mode

A single chip router for a multiplex communication network comprises a packet memory for storing data packets, a Reduced Instruction Set Computer (RISC) processor for converting the packets between a Local Area Network (LAN) protocol and a Wide Area Network (WAN) protocol, a LAN interface and a WAN interface. A Direct Memory Access (DMA) controller transfers packets transferring packets between the packet memory and the LAN and WAN interfaces. A packet attribute memory stores attributes of the data packets, and an attribute processor performs a non-linear hashing algorithm on an address of a packet being processed for accessing a corresponding attribute of said packet in the packet attribute memory. An address window filter identifies the address of a packet being processed by examining only a predetermined portion of said address, and can comprise a dynamic window filter or a static window filter.

Single chip network router

An adaptive error detection and correction apparatus for an Asynchronous Transfer Mode (ATM) network device comprises a sensing unit for sensing a congestion condition in the ATM network and a global pacing rate unit for adaptively reducing a maximum allowable transmission ratio of ATM cells containing information to idle ATM cells in response to a sensed congestion condition. A processor stores a number corresponding to a relatively high maximum allowable transmission ratio in the global pacing rate register in the absence of a sensed congestion condition, and stores a number corresponding to a relatively low maximum allowable transmission ratio in the global pacing rate register in response to a sensed congestion condition. A controller adjusts the maximum allowable transmission ratio in accordance with the number stored in the global pacing rate register. A plurality of peak pacing rate counters reset to predetermined values upon decrementation to zero, the predetermined values corresponding to service intervals for segmentation of Conversion Sublayer Payload Data Unit (CD-PDU)s. The processor further comprises means for assigning the counters to selected CD-PDUs, and sensing the counters to determine whether or not segmentation of said selected CD-PDUs is within the respective service intervals. The apparatus further comprises a channel group credit register having bits corresponding to the respective counters.

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Pleasanton, CA, United States of America

D Tony Stelliga