Interval Research Corporation

Other

Vulcan Patents LLC

D Robert Hoover

Krasimir D Kolarov

William C Lynch

William J Arrighi

A method and system to use floating differential output amplifiers wired in series and parallel to achieve arbitrary output drive voltage and current for the applications load. One embodiment includes the use of multiple differential amplifiers wired in series to generate a high voltage differential amplifier, while only partially using no-feedback buffer amplifiers and obtaining performance equivalent to an implementation that uses only buffer amplifiers. This is achieved by forcing the mismatch errors of conventional amplifiers to become power supply ripple. A second embodiment includes the use of a power supply centering technique to implement a floating asymmetrical differential amplifier. A third embodiment includes the use of multiple floating differential amplifiers, sharing a common power supply with individual biasing and isolation of each section of the amplifier, to allow high power amplifiers to be built with an arbitrary number of low power modules.

Floating differential amplifier architectures

A method and system to use voltage isolated and floating differential output amplifiers wired in series and parallel to achieve arbitrary output drive voltage and current for the applications load. Embodiments use multiple voltage-isolated and linearized devices to enable dynamically modifiable, Class A, Class B, and Class AB topologies of predetermined voltage and current performance. Embodiments can correct an output by linearizing one or more devices in a circuit by utilizing a linearization module (e.g., including one or more digital lookup tables, an error simulation circuit, or an equivalent) to linearize at least one parameter of at least one device in the circuit.

High voltage, high current, and high accuracy amplifier

A method and system to use voltage isolated and floating differential output amplifiers wired in series and parallel to achieve arbitrary output drive voltage and current for the applications load. A second embodiment uses multiple matched voltage-isolated and floating differential output amplifiers in a single chassis to enable selection between a multi-channel amplifier and a high current and/or high voltage mono amplifier. A third embodiment uses a step-up transformer and paralleled unity-gain buffer amplifiers, on input and/or output stages, to produce a zero feedback, high performance, high drive amplifier. A fourth embodiment uses a high voltage unity-gain driver amplifier to bias a unity-gain buffer amplifier and its power supply to achieve an ultra low distortion high voltage buffer amplifier. A fifth embodiment uses multiple voltage-isolated and linearized devices to enable dynamically modifiable, Class A, Class B, and Class AB topologies of predetermined voltage and current performance. A sixth embodiment corrects an output by linearizing one or more devices in a circuit by utilizing a linearization module (e.g., including one or more digital lookup tables, an error simulation circuit, or an equivalent) to linearize at least one parameter of at least one device in the circuit.

Decompressing compressed video information using relatively less temporary storage is disclosed. A compressed bit stream of video information including a compressed portion is received. A reverse combination in the transform domain is performed on the compressed portion to produce two corresponding portions of video information, where the two portions represent the compressed portion in a less compressed form. The two portions of video information are temporarily stored as a reverse combination is being performed. One of said two portions of video information is transformed, decoded, and decompressed to produce a decompressed portion of video information. The decompressed portion of video information is output.

Storage reduction during compression

A technique for compressing video images uses temporary compression of blocks during compression, integrated color rotation of compressed images, direct compression of a composite video signal, and border filters to allow blocks to be compressed independently. Temporary compression reduces storage needed in an integrated circuit. An incoming frame is compressed block-by-block and placed in temporary storage. A corresponding block of a later frame is also compressed. Both blocks are decoded back into the transform domain and the two blocks are compared in the transform domain. Color rotation on compressed color information is integrated with overall compression and is performed upon the chrominance transform pyramids after transformation of the video signal rather than performing a rotation on the raw signal itself. Color rotation is performed at any stage and uses serial multiplication (shift and add) for more efficient processing, rather than using parallel multiplication. A composite video signal including both color and black and white information is compressed directly without separating the color information from the black and white. A sequence of passes separates the luminance and chrominance information from the composite video signal and demodulates the color carrier to separate out color information. Blocks of information are treated independently using a modified 2-6 Biorthogonal filter to reduce complexity, to reduce hardware needed and to reduce blocking artifacts. The technique identifies and compresses composite video, S video, and component video signals, and is applicable to low bit rate video applications.

Compression of combined black/white and color video signal

Color rotation integrated with compression of video signal

A motion wavelet transform zero tree codec achieves high compression and is implemented in hardware of modest size and at very low cost. A wavelet transform is combined with a tree walk technique for encoding the resulting wavelet coefficients. A 2-6 wavelet transform is used. Wavelet coefficients from the transform are represented in a pyramid of wavelet coefficients. An array of zero trees are formed from the pyramid to hold the wavelet coefficients, one coefficient to each node. Significance values for each node are calculated to assist with the tree walk and encoding. Each zero tree is traversed to produce an output of encoded bits. Encoded bits are output directly during the tree walk.

Growing community of inventors

Cupertino, CA, United States of America

D Robert Hoover