Intel Corporation

D Michael Bell

Mark A Gonzales

Susan S Meredith

Anil Vasudevan

William T Futral

Sujoy Sen

Stephen S Pawlowski

Peter D MacWilliams

Parthasarathy Sarangam

Suvansh Krishan Kapur

Kevin Koschoreck

David W Archer

Srinand Venkatesan

Steve Pawlowski

Doug Moran

In one embodiment, a data movement module (DMM) may receive a command to copy data from a source buffer to a destination buffer. One or more cache lines corresponding to addresses of the source buffer and the destination buffer may be invalidated. Also, an entry may be added to a queue to indicate that the command to copy is completion pending.

Copy on access mechanisms for low latency data movement

Some embodiments include apparatus and method having a register circuit to receive a first portion of a packet from an input/output device, cache memory circuit to receive a second portion of the package, and a processing unit to process at least one of the first and second portions of the packet based on instructions in the processing unit. The processing unit and the register circuit reside on a processor. The first portion of the packet is placed into the register circuit of the processor, bypassing a memory device coupled to the processor. The second portion of the packet is placed into the cache memory circuit of the processor, bypassing the memory device.

Method and apparatus to reduce latency and improve throughput of input/output data in a processor

A system and method for sending device specific data in a bus transaction. A device configurable field is preallocated in a packet sent by the sending device to a receiving device. The sending device can configure the data to be stored in the device configurable field. Upon receipt of the packet, the receiving device generates a response packet in which the contents of the device configurable field is simply copied into a corresponding field in the response packet.

Method and apparatus for providing and embedding control information in a bus system

A synchronous bus system that enables the bus lengths between devices to be extended such that the timing budget is more than one clock cycle. A reset process resets the transmission and reception circuitry and both circuitry function according to prespecified parameters relative to the deassertion of the reset signal such that the amount of logic required to latch and sample the data is minimized. As the timing budget is not limited to one clock cycle, devices can be spaced further apart providing more physical space for devices. Furthermore, skew sensitivity is reduced as to the skew is distributed over multiple clock periods.

Fast 16 bit, split transaction I/O bus

A bus bridge receives an inbound read request from a master. In response to the read request, the bridge transmits multiple (e.g., two) read request packets to fetch data. The fetched data is stored in the bridge when it returns. When the master returns for its data, the data from each packet is transferred to the master if the data is valid. By issuing two smaller read request packets in response to an inbound read request, inbound read latency is reduced. In addition, if only a single master is being serviced, the system speculatively prefetches data for the master when the master returns to receive its data. Also, if the master is disconnected before completing the data transfer, the data can be subsequently restreamed from the bridge if the data is still valid when the master reconnects.

Computer system having improved data transfer across a bus bridge

The invention, in one embodiment, is a method for accessing memory. The method includes programming a remote DMA engine from a destination; accessing data in the memory with the DMA engine, the DMA engine operating as programmed by the destination; and transferring the accessed data to the destination.

Destination controlled remote DMA engine

A synchronous bus system that enables the bus lengths between devices to be extended such that the timing budget is more than one clock cycle. A reset process resets the transmission and reception circuitry and both circuitry function according to prespecified parameters relative to the deassertion of the reset signal such that the amount of logic required to latch and sample the data is minimized. As the timing budget is not limited to one clock cycle, devices can be spaced further apart providing more physical space for devices. Furthermore, skew sensitivity is reduced as the skew is distributed over multiple clock periods.

Split transaction I/O bus with pre-specified timing protocols to synchronously transmit packets between devices over multiple cycles

A computer system includes a host processor coupled to a host bus. A bridge controller is coupled to the host bus and to a plurality of first buses. The computer system also includes one or more bus bridges, each coupled to the bridge controller via one or more of said first buses. Each bus bridge is connected to one or more second buses. Either the first buses or the second buses are each configurable in either an independent mode in which the bus operates independently, or a combined mode in which two or more of said first buses or said second buses are combined to create a single bus.

Scalable computer system

A bus expander bridge is provided for interfacing first and second external buses (such as PCI buses) to a third bus. The bus expander bridge is configurable in either an independent mode in which the first and second external buses operate independently and a combined mode in which the first and second external buses are combined to create a single bus. The bus expander bridge includes a first set of data queues for routing data between the first external bus and the third bus, and a second set of data queues for routing data between the second external bus and the third bus. The bus expander bridge also includes a controller coupled to the first and second sets of data queues and operating the first and second sets of data queues in parallel for the independent mode. The controller routes even addressed data through the first set of data queues and routes odd addressed data through the second set of data queues for the combined mode.

Dual mode bus bridge for computer system

A system and method for controlling the flow of information between devices. A count is maintained representative of requests issued by a first device. The count is incremented for each packet issued by a first device and decremented for each packet received at the first device. A maximum buffer count, which corresponds to the capacity of the buffer is used to perform flow control by determining when the maximum buffer count is to be exceeded by the issuance of a packet by the first device. If the count is to be exceed, issuance of packets by the first device is prevented until the maximum buffer count will not be exceeded by issuance of the packet.

System and method of flow control for a high speed bus

Method and apparatus for programming a remote DMA engine residing on a

A computer system includes a host processor coupled to a host bus. The computer system also includes a memory system coupled to the host bus, and an I/O bridge controller coupled to the host bus and including a plurality of ports. An I/O bus bridge is provided that is hot plug connectable to at least one of the bridge controller ports via one or more first buses. There are one or more second buses coupled to the I/O bus bridge.

Hot plug connected I/O bus for computer system

The dual mode bus bridge accommodates either two 64-bit personal computer interface (PCI) buses or four 32-bit PCI buses. In either case, only a single load is applied to the host bus. The dual mode bridge includes a bridge controller unit connected to a pair of expansion bridge units by respective internal buses. Each expansion bridge unit includes two sets of 64-bit wide queues and buffers. For 32-bit PCI operation, the two sets of queues and buffers are operated in parallel. For 64-bit PCI operation, the two sets of queues and buffers are linked together so as to appear in series to provide a single queue structure having twice the depth of the separate queue structures for a 32-bit mode operation. As such, undue duplication of queue and buffer resources is avoided. Method and apparatus embodiments of the invention are described.

Dual mode bus bridge for interfacing a host bus and a personal computer

A bus bridge situated between two buses includes two queues: an outbound request queue and an inbound request queue. Requests originating on the first bus which target a destination on the second bus are placed into the outbound request queue. Requests originating on the second bus which target a destination on the first bus are placed into the inbound request queue. A transaction arbitration unit (TAU) within the bridge maintains transaction ordering and avoids deadlocks. The TAU determines whether requests can be placed in the inbound request queue. The TAU also determines whether requests originating on the first bus can be responded to immediately or whether the agent originating the request must wait for a reply. In addition, the TAU includes logic for determining whether a request in the outbound request queue can be executed on the second bus. The TAU determines whether posting to the inbound request queue is enabled or disabled; whether any posted transactions exist in the inbound request queue; and whether ownership of the second bus is available.

Growing community of inventors

Beaverton, OR, United States of America

D Michael Bell