Vlsi Technology, Inc.

Koninklijke Philips Corporation N.v.

Microchip Technology Inc.

Nxp B.v.

Vsli Technology, Inc.

D C Sessions

Timothy A Pontius

David R Evoy

Paul S Levy

Joseph W Triece

Franklyn H Story

James E Bartling

Yong Yuenyongsgool

Gregory Ehmann

Rodney J Pesavento

Gregg Lahti

John C Ciccone

Elie Khoury

Elie Georges Khoury

Mark Johnson

Sung-Hun Oh

Jerry Michael Rose

Tim Wilson

David Otten

Robert J Caesar, Jr

Arjan Bink

Ivan Svestka

Paul Reeves Auvil, Iii

James Muha

A voltage regulator for controlling an output device in accordance with embodiments includes an error amplifier; a controlled conductance output device; and a load predicting circuit; wherein an output of the error amplifier and an output of the load predicting circuit are summed to control the output device.

Capless voltage regulator using clock-frequency feed forward control

A common (ground) of a low voltage regulator is connected to a virtual common (ground) of an integrated circuit device that is also connected to transistor sources but isolated from a true ground connected to the substrate of the integrated circuit device. The regulated output voltage from the low voltage regulator rises the same as the virtual ground voltage rises when back-biased sufficient to reduce leakage current to an acceptable level in a given process technology. Therefore, the output of the low voltage regulator will maintain a normal operating voltage for the logic during a power saving back-biased condition.

Using low voltage regulator to supply power to a source-biased power domain

A microcontroller or integrated system has a bus, a plurality of peripheral devices each one coupled with the bus, a non-volatile memory, and a state machine coupled with the non-volatile memory and being operable to initialize the peripheral devices by reading initialization information from the non-volatile memory and writing it to the peripheral devices.

Dynamic state configuration restore

An integrated circuit device has a primary voltage regulator and an ultra-low power secondary voltage regulator. The ultra-low power secondary voltage regulator supplies voltage to certain circuits used for providing data retention and dynamic operation, e.g., a real time clock and calendar (RTCC) when the integrated circuit device is in a low power sleep mode. The primary voltage regulator provides power to these same certain circuits when the integrated circuit is in an operational mode.

Data retention secondary voltage regulator

The present invention relates to emphasizing and de-emphasizing of an analog data signal. Using a main analog driver a data signal indicative of bit values of binary data is converted into a first analog data signal. A second data signal is determined by delaying the data signal a predetermined time interval and inverting the delayed data signal. Using a de-emphasis driver, the second data signal are converted into a second analog data signal, wherein the second analog data signal is additive to the first analog data signal if the data signal and the second data signal are indicative of a same bit value, and wherein the second analog data signal is subtractive to the first analog data signal if the data signal and the second data signal are indicative of an opposite bit value. The first analog data signal is emphasized or de-emphasized by superposing the first analog data signal and the second analog data signal.

High speed driver equalization

A high resolution digital-to-analog converter comprises a programmable n-bit current digital-to-analog converter (IDAC), an m-bit programmable counter/timer, an integrator that converts the IDAC constant current charging a capacitor over time into an a precision (high resolution) analog voltage, and a sample and hold circuit for storing the precision analog voltage. The constant current from the IDAC is applied to the integrator for a time period determined by the programmable counter/timer, then the sample and hold circuit will sample the final voltage on the capacitor and store it as an analog voltage. The analog voltage resolution of this high resolution digital-to-analog converter is n+m bits or binary 2. In addition, a plurality of sample and hold circuits may be utilized for maintaining a plurality of analog output voltages.

Current-time digital-to-analog converter

A high-speed parallel data communication approach overcomes data skewing concerns by concurrently transmitting data in a plurality of multiple-bit groups and, after receiving the concurrently-transmitted data, realigning skew-caused misalignments between the groups. In one particular example embodiment, for each group, an arrangement transfers the data in parallel and along with a clock signal for synchronizing digital data. The transferred digital data is synchronously collected via the clock signal for the group. At the receiving module, the data collected for each group is aligned using each group's dedicated clock signal. Skew across clock-domain groups is tolerated and overcome by processing the data and the skew first within each clock domain group, and then between groups.

Parallel data communication realignment of data sent in multiple groups

A programmable speaker uses characterization data stored within the memory of the speaker and digital signal processing (DSP) to digitally perform transform functions on input audio signals to compensate for speaker related distortion and listening environment distortion. In a manufacturing environment, a non-intrusive system and method for tuning the speaker is performed by applying a reference signal and a control signal to the input of the programmable speaker. A microphone detects an audible signal corresponding to the input reference signal at the output of the speaker and feeds it back to a tester which analyzes the frequency response of the speaker by comparing the input reference signal to the audible output signal from the speaker. Depending on the results of the comparison, the tester provides to the speaker an updated digital control signal with new characterization data which is then stored in the speaker memory and used to again perform transform functions on the input reference signal. The tuning feedback cycle continues until the input reference signal and the audible output signal from the speaker exhibit the desired frequency response as determined by the tester. In a consumer environment, a microphone is positioned within selected listening environments and the tuning device is again used to update the characterization data to compensate for distortion affects detected by the microphone within the selected listening environment.

Intelligent speaker training using microphone feedback and pre-loaded templates

In one example embodiment, data is transferred at high speeds over a parallel data bus without loss of data integrity by transferring the data encoded with the quantity of ones relatively the same as the quantity of zeroes. Consistent with one embodiment of the present invention, a bus-interface circuit encodes a set of X data bits into a set of Y data bits, where Y is greater than X. The encoding is implemented to approximately balance the number of ones and the number of zeroes in each set to be transmitted. A specific example application involves encoding the set of X data bits so that there is a balanced number of ones and zeroes in the set of Y data bits. In certain applications, the present invention is implemented to reduce current flow between transmitting and receiving modules and thereby reduce EMI, reduce the number of power pins required for the bus interface, and/or reduce the I/O delay and the skew from voltage sag in the signals passed over the parallel data bus.

Parallel communication based on balanced data-bit encoding

A method and arrangement of transferring data at high speeds over a parallel data bus provides for calibration of the data without interrupting the data communication. Consistent with one aspect of the present invention, a method of parallel data communication is provided for a circuit arrangement including a parallel arrangement of data paths for passing data in parallel between at least two nodes. The method compares a sequence of data over an additional calibration/spare path relative to a matched sequence of data being passed on one of the multiple paths. In response to detecting skewed data, the transmission time for the subject path is adjusted in response to the comparison. Other example aspects of the invention are directed to procedures for rotating the calibration procedure through each of the data paths while using the spare to maintain communication integrity, and various embodiments for controlling the calibration procedure and for detecting whether the data is skewed.

Real-time channel calibration method and arrangement

A low pin count, moderate speed serial data bus that has a variable width for the transfer of data between devices of a computer system. The serial data bus can be selectively configured to be 1-bit, 4-bit, 8-bit or 16-bit wide. Data (including bus commands and addresses) carried by wider parallel buses are serialized into data blocks, which are then transferred by the serial data bus at a high speed. One feature of the present invention is that the pin count requirement for the present invention is low: only four control pins are required for controlling the data transfer mechanisms of the data bus. Another significant feature of the present invention is that the host and companion interfaces of the serial data bus can have non-matching widths. To allow for host and companion interfaces with non-matching widths, an initialization protocol is used to establish the effective width of the data bus at power-on reset.

System bus with a variable width selectivity configurable at initialization

A CMOS wave shaping buffer circuit comprises two CMOS inverter stages connected as a non-inverting buffer. In addition, the two stages are further coupled by way of their supply connections to produce a positive feedback from the second stage to the first whenever both stages are driven to a linear state, that is both transistors of each stage are &ldquo;ON&rdquo;. The positive feedback prevents the output stage from remaining in a logically ambiguous state, but forces crisp transitions from one state to another even for slowly changing input signals.

CMOS waveshaping buffer

A voltage-buffer circuit for changing an input signal at a first voltage range to an output signal at a second voltage range. In one embodiment, the voltage-buffer circuit is comprised of an input lead for receiving an input signal at a first voltage range, a plurality of transistors coupled to the input lead, and an output lead coupled to the plurality of transistors. The purpose of the transistors is to convert the input signal at the first voltage range to an output signal at a second voltage range. The output lead is for receiving the output signal at the second voltage range from said plurality of transistors. The plurality of transistors are arranged into a plurality of stages, with at least one of the transistors having a gate oxide of a first thickness and at least one of the transistors having a gate oxide of a second thickness, where the first thickness is less than said second thickness.

CMOS high-to-low voltage buffer

A high differential impedance load device. The present invention recites a load device including a first lead, a second lead, a first current mirror, a second current mirror, and a third lead. First lead, second lead, and third lead are coupled to first current mirror and second current mirror such that a current sunk on first lead is approximately equal to a current sunk on second lead. Third lead represents a reference voltage which is ground.

High differential impedance load device

A programmable n stage shift counter divider circuit includes a plurality of n flip-flops arranged in cascade from a first stage to an nth stage. The data inputs of each of the flip flops are coupled with the output of the next preceding stage through corresponding OR gates. A source of preload signals is coupled with the second inputs of the OR gates; and a combined trap detector and terminal count detector has inputs coupled with the outputs of the last n-1 stages of the shift counter circuit and an output coupled with the source of pre-load signals to operate it.

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Phoenix, AZ, United States of America

D C Sessions