Lattice Semiconductor Corporation

Cyrus Y Tsui

Albert L Chan

Ju Shen

Rafael Czernek Camarota

Kapil Shankar

Satwant Singh

Allan Thomas Davidson

Clement Lee

Jason Cheng

Bradley Felton

Ming C Hsu

Howard Y M Tang

Om P Agrawal

Howard H Tang

Jack Tim Wong

Chan-Chi Jason Cheng

Cheng-Yuan Michael Wang

Benny Ma

Sam Tsai

Howard Y Tang

Stanley J Kopec, Jr

Jerome Connelly Farmer

Chanchi J Cheng

Albert Chen

Howard S Tang

An ASIC conversion of a programmable logic device (PLD) is provided. The PLD includes a plurality of logic blocks coupled together by a PLD routing structure. The ASIC includes a plurality of logic blocks corresponding on a one-to-one basis with logic blocks in the PLD and a routing structure corresponding to the programmable routing structure of the PLD. Vias or traces are selectively placed in the ASIC so that logical behavior of its logic blocks matches that implemented in the PLD and the signal propagation delay through the ASIC matches the delay through the PLD.

Delay-matched ASIC conversion of a programmable logic device

A programmable device with logic blocks is configured to cascade product terms from one logic block to another to increase the logical input width of the product terms. Each logic block may produce a plurality of product terms based upon the selection of inputs from a routing structure. Logic blocks configured to receive cascaded product terms includes a plurality of AND gates corresponding to the plurality of product terms.

Programmable logic device with enhanced wide input product term cascading

An integrated circuit includes non-volatile and volatile memory, with the volatile memory controlling the integrated circuit's functionality. Various techniques are disclosed for programming the different types of memory through one or more data ports to provide in-system programmability and dynamic reconfigurability. External configuration devices are not required if the data from the non-volatile memory is transferred directly to the volatile memory.

Non-volatile and reconfigurable programmable logic devices

A programmable device and method with generic logic blocks. Each generic logic block is configurable to perform product term logic functions and memory functions, such as RAM, dual-port RAM, ROM, CAM, FIFO and switch.

Device and method with generic logic blocks

An improved programmable logic device includes a set of I/O cells, a set of logic blocks, and a routing pool that provides connections among the logic blocks and the I/O cells. At least one of the logic blocks includes a programmable logic array that generates product term output signals on product term output lines. A first product term summing circuit has input terminals, at least one of which is coupled to a product term output line. The first product term summing circuit generates an output signal at an output terminal in response to at least one product term output signal. Likewise, a second product term summing circuit has input terminals, at least one of which is coupled to a product term output line. The second product term summing circuit generates an output signal at an output terminal in response to at least one product term output signal. The logic block further includes first and second output lines and a first programmable switching device that programmably couples the first output line to the output terminal of either the first or the second product term summing circuit. The logic block further includes a second programmable switching device that programmably couples the second output line to the output terminal of either the first or the second product term summing circuit. The programmable logic device has increased functional capacity. In addition, generating an interconnect solution to program the programmable logic device is made simpler by the present invention.

Programmable logic device

An in-system programmable (ISP) system can be programmed by remote access from a host programming system. The remote access can be accomplished over a wired data network, a wireless data network, a radio channel, or any combination of the above. In the ISP system, an ISP controller receives control and programming data through the access interface to program ISP devices in accordance with ISP programming conventions. The ISP controller can be provided by an integrated circuit having a microprocessor core.

Simultaneous wired and wireless remote in-system programming of multiple remote systems

An input/output circuit in an In-system programmable (ISP) logic device allows an output signal from a boundary scan register to be provided as output during programming operations of said ISP logic device. Thus, the ISP logic circuit can provide valid data output to other circuits interfaced to the ISP logic circuit during programming of the ISP logic device, thereby obviating a need to reset the system after reprogramming of the ISP logic device.

Method and structure dynamic in-system programming

Method and structure for dynamic in-system programming

An improved programmable logic device that generates output signals skewed in time includes a set of I/O cells and first and second logic circuits. Each logic circuit generates a logic output signal on a respective output line coupled to at least one of the I/O cells. A first delay element coupled to the output line of the first logic circuit is programmably operable to delay the output signal of the first logic circuit relative to the output signal of the second logic circuit in response to a first delay control signal. A second delay element coupled to the output line of the second logic circuit is programmably operable to delay the output signal of the second logic circuit relative to the output signal of the first logic circuit in response to a second delay control signal. Control circuitry generates the first and second delay control signals so as to prevent simultaneous switching of the logic output signals of the first and second logic circuits. This invention may be used to delay output signals which are not time-critical, allowing fast switching of the limited number of time-critical macrocell output signals.

A method for minimizing instantaneous currents ina signal bus is disclosed. The method involves providing a programmable delay element in each of the signal buffers driving the signal on the bus. The programmable delay element in each signal buffer is selectable enabled to include a predetermined time delay. The method involves programming the delay elements in a selected group of the signal buffers t includde the predetermined time delay, so that the selected group of signal buffers each generate an output signal switching after the predetermined delay relative to the switching of output signals generated by other signal buffers.

Method for minimizing instantaneous currents when driving bus signals

A programmable integrated circuit device includes a plurality of output terminals, each output terminal for use in transmitting a respective output signal. Timing control circuitry is connected to the output terminals. The timing control circuitry is operable to delay the output signal on each output terminal and is further operable to control a slew rate of the output signal on each output terminal.

Programmable integrated circuit device with slew control and skew control

A programmable logic device includes a global clock structure and a plurality of localized clock structures. Each localized clock structure distributes a respective localized clock signal to a corresponding portion of the programmable logic device. The global clock structure distributes a global clock signal to all portion of the programmable logic device.

Combination of global clock and localized clocks

A programmable logic device includes a global clock structure and a plurality of localized clock structures. Each localized clock structure distributes a respective localized clock signal to a corresponding portion of the programmable logic device. The global clock structure distributes a global clock signal to all portions of the programmable logic device.

An improved programmable logic device is disclosed. In one embodiment, the programmable logic device includes a plurality of I/O cells and a plurality of logic block clusters. Each logic block cluster has a set of logic blocks and a cluster routing pool, which provides programmable connections among the logic blocks and the I/O cells. A global routing pool provides programmable connections among the logic block clusters and the I/O cells. Each logic block includes a programmable logic array with a plurality of outputs. A product term sharing array in the logic block has a plurality of bus lines, each of which is coupled to at least one of the outputs of the programmable logic array. The product term sharing array also includes a plurality of output lines, each of which is coupled to a plurality of programmable interconnections that each provide a connection to one of the bus lines. Each output line of the product term sharing array is coupled to the same number of programmable interconnections. The logic block also includes a register coupled to at least one of the output lines of the product term sharing array. The register has a data input terminal and a data output terminal. First and second output multiplexers each have a first input terminal coupled to the data input terminal of the register and a second input terminal coupled to the data output terminal of the register.

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Los Altos, CA, United States of America

Cyrus Y Tsui