Lsi Logic Corporation

Cyrus C Cheung

Keith D Au

Darren Jones

A system which simplifies the clock tuning process for a clock buffer tree. Essentially, a clock buffer tree is provided where the clock buffer tree includes clock buffers of different strengths. The different strength clock buffers which are in the clock buffer tree have the same pin-out configuration. Hence, it is easy and straightforward to upsize or downsize any of the clock buffers in the clock buffer tree, and it is guaranteed that the new cell will fit into the old cell's slot in the tree. Since none of the nets need to be modified, consistent timing results are achieved. Moreover, the new timing for the modified clock buffer can be anticipated because its wire loading does not change at all. The ease of clock tuning makes it much easier to design clock buffer trees and layouts, and allows the overall design to be completed faster and easier.

Uni-sized clock buffers

A clock gating cell and a method of manufacturing the same. In one embodiment, the clock gating cell includes: (1) gate signal and clock signal inputs configured to receive gate enable and clock input signals, respectively, and (2) a gated clock signal output configured to generate a gated clock signal that is a function of states of the gate enable and clock signals, the clock gating cell treated as an atomic entity in a cell library.

Clock gating cell for use in a cell library

A computer network is provided with a low-complexity sequence identification number determination method. In one embodiment, the computer network comprises a local node coupled to a remote node by a serial communications link to conduct data exchanges with the remote node. Each data exchange is provided with an exchange identification number, and each data exchange is made up of sequences of consecutive frames. Each sequence transmitted from the local node is assigned a sequence identification number by the local node. To maintain the uniqueness of the serial identification numbers of concurrently active sequences, a portion of each serial identification number is set equal to the exchange identification number of the data exchange of which the sequence is a part. The exchange identification number may be one assigned to the exchange by the remote node. In one implementation, the sequence identification number is a byte having the six most significant bits set equal to the exchange identification number. The local node may include a serial communications transceiver coupled to a transmit controller and a receive controller. The transmit controller would then generate frame headers for each data frame and determine the sequence identification number to be included.

System and method for establishing unique sequence identification in an

A memory interface for synchronous burst SRAMs is provided. In one embodiment, an information processing system comprises a processor and a memory coupled by a memory interface. The memory interface includes a left data latch and a right data latch. The left data latch latches and holds data provided by the memory until the processor accepts it. The right data latch latches and holds data provided by the memory if the left data latch is already latched. Each data latch is freed after its contents have been provided to the processor. A multiplexer is included to steer the least-recently latched data to the processor. The latches and multiplexer are controlled by an interface controller which tracks the state of the latches and the order in which they latched. The interface controller generates control signals in response to the state of the latches and signals from the processor and the memory. The memory interface advantageously operates to maintain the availability of addressed data from memory during interruptions of the processor so that no additional memory access cycles are lost when memory access is restarted by the processor.

Growing community of inventors

Hercules, CA, United States of America

Cyrus C Cheung