Adeia Semiconductor Bonding Technologies Inc.

International Business Machines Corporation

Nutool, Inc.

Novellus Systems Incorporated

Asm Nutool, Inc.

Other

Adeia Semiconductor Technologies LLC

Invensas Bonding Technologies, Inc.

Invensas LLC

Asm America, Inc.

Adeia Semiconductor Inc.

Emekatech, LLC

Uzoh, Cyprian Emeka

Nchekwube, Emeka

Cyprian Emeka Uzoh

Rajesh Katkar

Guilian Gao

Belgacem Haba

Bulent Mehmet Basol

Homayoun Talieh

Charles Gerard Woychik

Liang Wang

Laura Wills Mirkarimi

Ilyas Mohammed

Gaius Gillman Fountain, Jr

Arkalgud R Sitaram

Terrence Caskey

Hong Shen

Daniel C Edelstein

Craig S Mitchell

Michael W Newman

Jeremy Alfred Theil

Pezhman Monadgemi

Vage Oganesian

Zhuowen Sun

Andrew Herbert Simon

Panayotis Constantinou Andricacos

Douglas W Young

Bongsub Lee

Paul M Enquist

Peter Stevens Locke

Piyush Savalia

Shaowu Huang

Gabriel Z Guevara

Konstantin Volodarsky

Boguslaw Nagorski

Rimma Volodarsky

Hariklia Deligianni

Javier A DeLaCruz

Chao-Kun Hu

Kenneth Parker Rodbell

Jalal Ashjaee

Patrick William Dehaven

Min Tao

John Owen Dukovic

Thomas Workman

Cyril Cabral, Jr

Hiroaki Sato

Christopher Vincent Jahnes

James M Harper

Wilma Jean Horkans

Joachim Norbert Burghartz

Emeka Nchekwube

Fatima Lina Ayatollahi

Kishor V Desai

Se Young Yang

Akash Agrawal

Chandrasekhar Mandalapu

Huailiang Wei

Yong Qin Chen

Scott Kevin Reynolds

Stephen Edward Greco

Ellis Chau

Reynaldo Co

Christopher Carr Parks

Lynne Marie Gignac

Sergey Savastiouk

Ron Zhang

Dale J Pearson

King-Ning Tu

James McKell Edwin Harper

Hung-Ming Wang

Valentin Kosenko

Steven H Boettcher

Sangil Lee

Kwong-Hon Wong

Jeffrey A Bogart

Wael Zohni

Alejandro Gabriel Schrott

Eugene John O'Sullivan

Yun-Yu Wang

Edward Crandal Cooney, Iii

Carlos Juan Sambucetti

Ashok S Prabhu

Philip Damberg

Madhav Datta

Vlasta A Brusic

John A Miller

Erick G Walton

Robert P Westerfield, Jr

Arnold Halperin

Serdar Aksu

Scott P McGrath

Eric Tosaya

Keith Thomas Kwietniak

Jeffrey R Marino

James Edward Fluegel

Stephen Alan Cohen

Jeff A Bogart

L Paivikki Buchwalter

Paul G Lindquist

Xuan Li

Dean S Chung

An MS&E alum contributes to tech and community

An element, a bonded structure including the element, and a method forming the element and the bonded structure are disclosed. The element can include a non-conductive region having a cavity. The element can include a conductive feature formed in the cavity. The conductive feature includes a center portion and an edge portion having first and second coefficients of thermal expansion respectively. The center and edge portions are recessed relative to a contact surface of the non-conductive region by a first depth and a second depth respectively. The first coefficient of thermal expansion can be at least 5% greater than the second coefficient of thermal expansion. The bonded structure can include the element and a second element having a second non-conductive region and a second conductive feature. A conductive interface between the first and second conductive features has a center region and an edge region. In a side cross-section of the bonded structure, there are more voids at or near the edge region than at or near the center region.

Expansion controlled structure for direct bonding and method of forming same

An element, a bonded structure including the element, and a method of forming the same are disclosed. The bonded structure can include a first element having a first nonconductive field region and a first conductive feature. A surface of the first nonconductive field region and a surface of the first conductive feature at least partially defining a bonding surface of the first element. The first conductive feature includes a first portion and a second portion over the first portion and at least partially defines the surface of the first conductive feature. The first portion includes aluminum. The first conductive feature has a continuous sidewall along the first portion and the second portion. The second portion includes different metal composition from the first portion or comprising fluorine at the surface of the first conductive feature. The bonded structure can include a second element having a second nonconductive field region and a second conductive feature. A surface of the second nonconductive field region is directly bonded to the first nonconductive field region without an intervening adhesive along a bond interface and a surface of the second conductive feature is directly bonded to the second conductive feature without an intervening adhesive along the bond interface.

Directly bonded metal structures having aluminum features and methods of preparing same

Representative techniques and devices including process steps may be employed to mitigate the potential for delamination of bonded microelectronic substrates due to metal expansion at a bonding interface. For example, a metal pad having a larger diameter or surface area (e.g., oversized for the application) may be used when a contact pad is positioned over a TSV in one or both substrates.

Metal pads over TSV

A microelectronic structure with through substrate vias (TSVs) and method for forming the same is disclosed. The microelectronic structure can include a bulk semiconductor with a via structure. The via structure can have a first and second conductive portion. The via structure can also have a barrier layer between the first conductive portion and the bulk semiconductor. The structure can have a second barrier layer between the first and second conductive portions. The second conductive portion can extend from the second barrier layer to the upper surface of the bulk semiconductor. The microelectronic structure containing TSVs is configured so that the microelectronic structure can be bonded to a second element or structure.

Structures with through-substrate vias and methods for forming the same

Representative implementations provide techniques and systems for processing integrated circuit (IC) dies. Dies being prepared for intimate surface bonding (to other dies, to substrates, to another surface, etc.) may be processed with a minimum of handling, to prevent contamination of the surfaces or the edges of the dies. The techniques include processing dies while the dies are on a dicing sheet or other device processing film or surface. Systems include integrated cleaning components arranged to perform multiple cleaning processes simultaneously.

Die processing

A bonding method can include polishing a first bonding layer of a first element for direct bonding, the first bonding layer comprises a first conductive pad and a first non-conductive bonding region. After the polishing, a last chemical treatment can be performed on the polished first bonding layer. After performing the last chemical treatment, the first bonding layer of the first element can be directly bonded to a second bonding layer of a second element without an intervening adhesive, including directly bonding the first conductive pad to a second conductive pad of the second bonding layer and directly bonding the first non-conductive bonding region to a second nonconductive bonding region of the second bonding layer. No treatment or rinse is performed on the first bonding layer between performing the last chemical treatment and directly bonding.

Direct bonding methods and structures

Representative techniques provide process steps for forming a microelectronic assembly, including preparing microelectronic components such as dies, wafers, substrates, and the like, for bonding. One or more surfaces of the microelectronic components are formed and prepared as bonding surfaces. The microelectronic components are stacked and bonded without adhesive at the prepared bonding surfaces.

Techniques for processing devices

Representative implementations of techniques and methods include chemical mechanical polishing for hybrid bonding. The disclosed methods include depositing and patterning a dielectric layer on a substrate to form openings in the dielectric layer, depositing a barrier layer over the dielectric layer and within a first portion of the openings, and depositing a conductive structure over the barrier layer and within a second portion of the openings not occupied by the barrier layer, at least a portion of the conductive structure in the second portion of the openings coupled or contacting electrical circuitry within the substrate. Additionally, the conductive structure is polished to reveal portions of the barrier layer deposited over the dielectric layer and not in the second portion of the openings. Further, the barrier layer is polished with a selective polish to reveal a bonding surface on or at the dielectric layer.

Direct hybrid bonding of substrates having microelectronic components with different profiles and/or pitches at the bonding interface

Representative implementations of techniques and devices provide seals for sealing the joints of bonded microelectronic devices as well as bonded and sealed microelectronic assemblies. Seals are disposed at joined surfaces of stacked dies and wafers to seal the joined surfaces. The seals may be disposed at an exterior periphery of the bonded microelectronic devices or disposed within the periphery using the various techniques.

Seal for microelectronic assembly

Through-dielectric-vias (TDVs) for 3D integrated circuits in silicon are provided. Example structures and processes fabricate conductive vertical pillars for an integrated circuit assembly in a volume of dielectric material instead of in silicon. For example, a block of a silicon substrate may be removed and replaced with dielectric material, and then a plurality of the conductive pillars can be fabricated through the dielectric block. The through-dielectric-vias are shielded from devices and from each other by an intervening thickness of the dielectric sufficient to reduce noise, signal coupling, and frequency losses. The through-dielectric-vias can provide improved stress management and reduced keep-out-zones, reduced via-to-via and via-to-device coupling because of relatively large dielectric spacing and low-k dielectrics that can be used, reduced parasitic capacitance, faster switching speeds, lower heat dissipation requirements, lower production costs, easy miniaturization that is scalable to large assemblies and interposers, and high performance stacked assemblies.

Through-dielectric-vias (TDVs) for 3D integrated circuits in silicon

Representative implementations provide techniques for processing integrated circuit (IC) dies and related devices, in preparation for stacking and bonding the devices. The disclosed techniques provide removal of processing residue from the device surfaces while protecting the underlying layers. One or more sacrificial layers may be applied to a surface of the device during processing to protect the underlying layers. Processing residue is attached to the sacrificial layers instead of the device, and can be removed with the sacrificial layers.

Processing stacked substrates

A method of direct hybrid bonding first and second semiconductor elements of differential thickness is disclosed. The method can include patterning a plurality of first contact features on the first semiconductor element. The method can include second a plurality of second contact features on the second semiconductor element corresponding to the first contact features for direct hybrid bonding. The method can include applying a lithographic magnification correction factor to one of the first patterning and second patterning without applying the lithographic magnification correction factor to the other of the first patterning and the second patterning. In various embodiments, a differential expansion compensation structure can be disposed on at least one of the first and the second semiconductor elements. The differential expansion compensation structure can be configured to compensate for differential expansion between the first and second semiconductor elements to reduce misalignment between at least the second and fourth contact features.

Dimension compensation control for directly bonded structures

Representative implementations of techniques and devices are used to reduce or prevent conductive material diffusion into insulating or dielectric material of bonded substrates. Misaligned conductive structures can come into direct contact with a dielectric portion of the substrates due to overlap, especially while employing direct bonding techniques. A barrier interface that can inhibit the diffusion is disposed generally between the conductive material and the dielectric at the overlap.

Diffusion barrier for interconnects

Reliable hybrid bonded apparatuses are provided. An example process cleans nanoparticles from at least the smooth oxide top layer of a surface to be hybrid bonded after the surface has already been activated for the hybrid bonding. Conventionally, such an operation is discouraged. However, the example cleaning processes described herein increase the electrical reliability of microelectronic devices. Extraneous metal nanoparticles can enable undesirable current and signal leakage from finely spaced traces, especially at higher voltages with ultra-fine trace pitches. In the example process, the extraneous nanoparticles may be both physically removed and/or dissolved without detriment to the activated bonding surface.

Reliable hybrid bonded apparatus

Growing community of inventors

San Jose, CA, United States of America

Cyprian Emeka Uzoh