Intergraph Corporation

Cynthia E Allison

Dale L Kirkland

Jeffrey Scott Ford

James Paul Turner

Joseph Clay Terry

A graphics accelerator includes a plurality of digital signal processors that are arranged in a self-regulating, peer-to-peer configuration. Accordingly, the processors cooperate to process, on a cyclical basis, each of a successive series of graphics requests received over a request bus. To that end, each processor includes a request bus, an input in communication with the request bus, and an output coupled to a sequencer for ordering graphics requests processed by the digital signal processors.

Peer-to-peer parallel processing graphics accelerator

A graphics processing accelerator has a plurality of digital signal processors that each have an output, and an input in communication with a request bus. The digital signal processors are arranged in a peer-to-peer configuration to process, on a cyclical basis, each of a successive series of graphics requests received over a request bus. The graphics processing accelerator also may have a sequencer in communication with each digital signal processor output for ordering graphics requests processed by the digital signal processors.

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Madison, AL, United States of America

Cynthia E Allison