Tandem Computers Incorporated

Compaq Computer Corporation, Inc.

Curtis Willard Jones, Jr

William P Bunton

William J Watson

David P Sonnier

Daniel L Fowler

Robert W Horst

David J Garcia

John C Krause

William F Bruckert

William Edward Baker

Frank A Williams

John Michael Brown

John D Coddington

Douglas E Jewett

Richard W Cutts, Jr

Susan S Meredith

Steven C Meyers

Geoffrey I Iswandhi

Stephen G Low

Patricia L Whiteside

Linda Ellen Zalzala

Randall G Banton

Paul N Hintikka

James Stevens Klecka

Gary F Campbell

Barry Lee Drexler

Harry Frank Elrod

Michael P Simpson

Self-checked, lock step processor pairs

A multiprocessor system includes a number of sub-processor systems, each substantially identically constructed, and each comprising a central processing unit (CPU), and at least one I/O device, interconnected by routing apparatus that also interconnects the sub-processor systems. A CPU of any one of the sub-processor systems may communicate, through the routing elements, with any I/O device of the system, or with any CPU of the system. The CPUs are structured to operate in one of two modes: a simplex mode in which the two CPUs operate independently of each other, and a duplex mode in which the CPUs operate in lock-step synchronism to execute each instruction of identical instruction streams at substantially the same time. Communications between I/O devices and CPUs is by packetized messages. Interrupts from I/O devices are communicated from the I/O devices to the CPUs (or from one CPU to another CPU) as message packets. CPUs and I/O devices may write to, or read from, memory of a CPU of the system. Memory protection is provided by an access validation method maintained by each CPU in which CPUs and/or I/O devices are provided with a validation to read/write memory of that CPU, without which memory access is denied.

Fail-fast, fail-functional, fault-tolerant multiprocessor system

A multiprocessor system includes a number of sub-processor systems, each substantially identically constructed, and each comprising a central processing unit (CPU), and at least one I/O device, interconnected by routing apparatus that also interconnects the sub-processor systems. A CPU of any one of the sub-processor systems may communicate, through the routing elements, with any I/O device of the system, or with any CPU of the system. Communications between I/O devices and CPUs is by packetized messages. Interrupts from I/O devices are communicated from the I/O devices to the CPUs (or from one CPU to another CPU) as message packets. CPUs and I/O devices may write to, or read from, memory of a CPU of the system. Memory protection is provided by an access validation method maintained by each CPU in which CPUs and/or I/O devices are provided with a validation to read/write memory of that CPU, without which memory access is denied.

Method of synchronizing a pair of central processor units for duplex,

Growing community of inventors

Austin, TX, United States of America

Curtis Willard Jones, Jr