Intel Corporation

Curtis Shirota

Suraj Sindia

Clark N Vandam

Suriya Kumar

Ricardo Ascazubi

Systems and methods for latch-up detection and mitigation. One aspect includes a method implemented in a system divided into a plurality of power blocks, where each power block is powered by a corresponding power rail and includes a voltage droop monitoring circuitry. The method comprises receiving frequency information from the plurality of voltage droop monitoring circuitries; normalizing the received frequency information from each of the plurality of voltage droop monitoring circuitries; creating a matrix of cross-correlation values based on the normalized frequency information between each pair of the plurality of power blocks; determining deviations in the cross-correlation values indicating an occurrence of voltage droop; determining an abnormal variation based on the determined deviations to identify a first power block, out of the plurality of power blocks, experiencing a latch-up event; and resetting power to the first power block without interrupting power to rest of the plurality of power blocks.

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Hillsboro, OR, United States of America

Curtis Shirota