Bae Systems Information and Electronic Systems Integration Inc.

Purdue Research Foundation

Curtis M Grens

Joseph D Cali

Richard L Harwood

Gary M Madison

James M Meredith

Paul D Zemany

Dimitrios Peroulis

Lawrence J Kushner

Steven E Turner

Gregory M Flewelling

Mark D Hickle

Jack Chuang

Eric J Naglich

Mark E Stuenkel

Thomas J Johnson

Michael Dimitri Sinanis

Souleymane Gnanou

Randall M White

Justin A Cartwright

Zachary D Schottmiller

A phase locked loop (PLL) control system includes a voltage-controlled oscillator (VCO) circuit including an inductor and a plurality of capacitors arranged in parallel with the inductor. Digitally enabling or disabling the capacitors in a thermometer coded manner via switches creates tuning states that provide additional frequency range, and each has a limited range of VCO frequency tuning. Slowly ramping the switched capacitance, by implementing the capacitor as a varactor, from one thermal code to the next, provides a wider continuous VCO frequency tuning range for use in the PLL. The slow transition between tuning states allows the PLL to remain in lock, useful under changing operating conditions. Specifically, under changing operating conditions, digital logic detects the PLL tuning control voltage approaching the edge of a VCO band and will add/reduce VCO capacitance effectively transitioning into the adjacent VCO band while the PLL maintains lock via its normal feedback loop.

Continuous tuning of digitally switched voltage-controlled oscillator frequency bands

A clock alignment system includes a first clock generator generating a first clock signal in a first clock domain and a second clock generator generating a second clock signal in a second clock domain slower than the first clock domain. A coarse delay-locked loop (DLL) generates third clock signals having corresponding phase offsets from the first clock signal, and a fine DLL generates a fourth clock signal by adjusting the phase of a selected one of the third clock signals. The second clock generator generates the second clock signal from the fourth clock signal. A phase detector compares phases of the first and second clock signals. A control circuit aligns the first and second clock signals by using the compared phases to select the third clock signal output by the coarse DLL, and control the phase adjustment by the fine DLL of this third clock signal.

Clock alignment system having a dual-loop delay-locked loop

Anti-jamming techniques are provided for RF receivers, such as those that operate in hostile environments. In some embodiments, the techniques are embodied in an anti-jam communications system configured with automatic gain control (AGC) that is complementary. The system includes a first AGC circuit prior to an interference suppression circuit and a second AGC circuit after the interference suppression circuit. The first AGC circuit operates to adjust the power level presented to the interference suppression circuit to facilitate interference cancellation. The second AGC circuit operates to maintain the original power level of the desired communications signal and prevent amplitude errors as the first AGC circuit responds to fluctuations in jammer signal power. The second AGC can be slaved to the first AGC circuit such that the sum of two gain values is held constant, according to some embodiments. In this manner, the first and second AGC circuits provide a complementary-AGC system.

Complementary automatic gain control for anti-jam communications

Techniques are provided for phase-locked loop (PLL) configuration, based on a calibrated lookup table (LUT). A methodology implementing the techniques according to an embodiment includes selecting one of a number of voltage controlled oscillators (VCOs) of the PLL, and selecting a tuning parameter to control the VCO. The method further includes testing the PLL, using multiple loop divider values, to determine a minimum and maximum value that define the lower and upper bounds of a range of loop divider values for which the PLL achieves a locked state while using the selected VCO and tuning parameter. The method further includes storing PLL configuration parameters to an entry in the configuration LUT, the PLL configuration parameters to include an identification of the selected VCO, the selected tuning parameter, the minimum loop divider value, and the maximum loop divider value. The method iterates using additional combinations of selected VCOs and tuning parameters.

Calibrated lookup table for phase-locked loop reconfiguration

An evanescent-mode cavity filter with an improved MEMS tuner design is disclosed. The MEMS tuner design allows for the independent control of individual poles in a multi-pole filter, which increases the adaptability of the filter in a crowded RF environment. The filter is further designed to minimize tuning voltages and hysteresis effects. A closed loop control system provides highly responsive tuning of the filter. The closed loop control allows for accurate and stable tuning that compensates for temperature and vibrational effects, while the tuner design enables fast tuning and significantly increases the resolution of the feedback measurement by eliminating charge buildup in the tuner substrate.

Tunable evanescent-mode cavity filter with closed loop control

Frequency divider techniques are disclosed which can be used to address two problems: when an incorrect division occurs if the modulus control changes before the divide cycle is complete, and when an incorrect division occurs due to a boundary crossing (e.g., power-of-2 boundary crossing in a fractional-N PLL application). In one embodiment, a frequency divider is provided comprising a plurality of flip-flops operatively coupled to carry out division of an input frequency, and configured to generate a modulus output and receive a divided clock signal of a previous cell. An additional flip-flop is selectively clocked off one of the modulus output or the divided clock of the previous stage, depending at least in part on a Skip control signal applied to a data input of the additional flip-flop, and is further configured to selectively reset the plurality of flip-flops to a state that will result in a correct divide ratio.

Multi-modulus divider with power-of-2 boundary condition support

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Manchester, NH, United States of America

Curtis M Grens