Nascentric, Inc.

University of Texas System

Cadence Design Systems, Inc.

Silicon Metrics Corporation

Curtis L Ratzlaff

John F Croix

Robert J Jones

Chanhee Oh

Nanda Gopal

Lawrence T Pillage

Ramon D Acosta

In one embodiment, a method comprises creating a simulation model for a column of bit cells in a memory, simulating the simulation model to generate a result; and displaying the result for a user. Each of the bit cells in the column is coupled to a different wordline, and the simulation model comprises one or more linear elements in place of a nonlinear element in each bit cell that is coupled to an inactive wordline. The one or more linear elements approximate a behavior of the nonlinear element while the wordline is inactive. A computer accessible storage medium storing a simulator that implements the method is contemplated, and the simulator itself is also contemplated, in various embodiments.

High speed memory simulation

In one embodiment, a method for simulating an electric circuit that is represented as one or more partitions, each partition comprising a plurality of constituents representing portions of the circuit, wherein at least one of the constituents is a variable constituent for which the corresponding portion of the electronic circuit includes non-linear behavior, comprises: determining a first matrix for the variable constituent, wherein the first matrix describes a system of equations that represents a behavior of the variable constituent; determining a second matrix for the partition, wherein the second matrix permits calculation of short circuit currents from open circuit voltages according to a node tearing analysis method; and simulating a timestep of the simulation, the simulating comprising iteratively solving a state of the partition using successive guesses of the state of the variable constituent, wherein each iteration comprises solving the variable constituent independently to generate the open circuit voltages using the first matrix, applying the second matrix to determine the short circuit currents, and resolving the variable constituent with the short circuit currents applied and the forcing functions disabled; converging to a solution during the iteratively solving; and solving the partition state for the timestep responsive to the convergence.

Using impedance (Z) parameters to augment circuit simulation

A system for analyzing a model of an electronic circuit, which includes at least one non-linear circuit element, includes a computer. The computer replaces the non-linear circuit element with a linearized circuit model that approximates a behavior of the non-linear circuit element. The computer also inserts into an element matrix a calculated value that corresponds to the linearized circuit model for a prescribed or desired time step. The computer further performs a numerical operation on the element matrix to effectively invert the element matrix.

Apparatus and methods for simulation of electronic circuitry

A system for analyzing an electronic circuit includes a computer. The computer obtains a description of the electronic circuit. The computer further analyzes the electronic circuit by using compiled static timing analysis (CSTA). Specifically, in one embodiment, the computer is configured to compile a timing model for the circuit responsive to the description of the circuit. The timing model comprises a description of a timing path and a description of an algorithm to evaluate the timing path. The computer is further configured to analyze a design that includes the circuit, wherein the analyzing comprises evaluating the timing model, and wherein evaluating the timing model comprises performing the algorithm to evaluate the timing path.

Apparatus and methods for compiled static timing analysis

Systems and methods are described for a circuit interconnect model compiler. A method includes providing extraction data from an interconnect; reading a dataset from said extraction data from said interconnect; reducing said dataset to form a model; evaluating said model for a set of conditions to obtain a solution; and writing said solution to an application. The systems and methods provide advantages in that the speed, reliability and accuracy of the design process are improved and the affect of circuit interconnects is taken into account.

Interconnect model compiler

A method and apparatus for simulating a microelectronic circuit or system includes the storing of a microelectronic circuit or system representation in a computer and then transforming the representation into an equivalent DC circuit containing resistive, capacitive and inductive elements. Then, a directed graph of the DC equivalent circuit is generated and a spanning tree is constructed therefrom. The spanning tree is then actually or virtually traversed to obtain multiple generations of circuit moments. The moments are then used to calculate the poles and residues for a given node and generate an approximate model of the circuit's transient response at that node. Moment shifting is used to provide for a stable approximate model. The actual residues corresponding to the coefficients of the time domain representation for the model can be calculated using the first q-1 moments. This constitutes a partial-Pade approximation.

Growing community of inventors

Austin, TX, United States of America

Curtis L Ratzlaff