Ahead Communications Systems, Inc.

Cuong T Luu

Ronald P Novick

John Cumberton

Stephen J Nichols

The invention utilizes two-stage shaping and two-priority queuing thereby allowing both shaped and unshaped virtual circuits to be provisioned in a single virtual path. For each VP, a separate dynamic buffer is set up for each shaped VC and unshaped VC within the VP. The shaped cells stored in dynamic buffers are dequeued via VC scheduling (first stage shaper) to a high priority queue according to the shaped VC contracts, and the unshaped cells stored in dynamic buffers are dequeued in a round robin manner to a low priority queue. The outputs of both the high priority queue and the low priority queue are passed to a second stage shaper where cells from the high priority queue are scheduled according to the VP contract, and cells from the low priority queue are also scheduled according to the VP contract, but only when VP bandwidth is not being used by the high priority cells. In order to avoid overrunning the high priority queue in the second stage, the iPSR (Peak Shaping Rate increment) of the CBR VCs in the VP is chosen to be the iSSR (Sustained Shaping Rate increment) of the VP. The iPSR of the CBR VCs in the VP can be chosen to be higher than the iSSR of the VP as long as cell loss is not experienced at the second stage caused by overrunning the high priority queue. In addition, the calculated bucket for CBR service in the first stage is made a function of the Peak Cell Rate (PCR) of the VP.

Multi-tiered shaping allowing both shaped and unshaped virtual circuits to be provisioned in a single virtual path

A modified UTOPIA interface for inter-board applications is provided where the address timing generated by a polling master is extended to be two clock cycles long with no NULL address being driven onto the address line in between addresses. Output and input circuitry is provided in conjunction with the polling master and user ATM boards to accommodate hot insertion and to help drive the circuit. The master preferably includes an outgoing address latch and address latch control associated with the address bus, and a register associated with the enable signal. The master also includes a hot insertion buffer on the incoming cell available signal. The user device(s) include hot insertion buffers on the address bus, the data bus, and the enable signal. A remapping function is also preferably provided in associated with the user board which permits the user board to map received addresses into desired addresses. With the extended address timing and the provided circuitry, a workable inter-board hot-insertable UTOPIA interface is established.

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Kensington, CT, United States of America

Cuong T Luu