Omnivision Technologies, Inc.

Cunyu Yang

Gang Chen

Dyson Hsinchih Tai

Duli Mao

Chen-Wei Lu

Qin Wang

Lindsay Alexander Grant

Zhiqiang Lin

Yuanwei Zheng

Cheng Zhao

Guannan Chen

Howard E Rhodes

Yin Qian

Hsin-Chih Tai

Tiejun Dai

Hui Zang

Sing-Chung Hu

Dajiang Yang

Oray Orkun Cellek

Chengming Liu

Jing Ye

Ping-Hsu Chen

Philip John Cizdziel

Eric Webster

Jiaming Xing

Xi-Feng Gao

A pixel includes a semiconductor substrate, a low-&#x3ba; dielectric, and a photodiode region in the semiconductor substrate. The semiconductor substrate has a substrate top surface that forms a trench. The trench extends into the semiconductor substrate and has a trench depth relative to a planar region of the substrate top surface surrounding the trench. The low-&#x3ba; dielectric is in the trench between the trench depth and a low-&#x3ba; depth with respect to the planar region. The low-&#x3ba; depth is less than the trench depth. The photodiode region is in the semiconductor substrate and includes (i) a bottom photodiode section beneath the trench and (ii) a top photodiode section adjacent to the trench. The top photodiode section begins at a photodiode depth, with respect to the planar region, that is less than the low-&#x3ba; depth, and extends toward and adjoining the bottom photodiode section.

Pixel, associated image sensor, and method

An image sensor includes a substrate. An array of photodiodes is disposed in the substrate. A plurality of spacers is arranged in a spacer pattern. At least one spacer of the plurality of spacers has an aspect ratio of 18:1 or greater. A buffer layer is disposed between the substrate and the spacer pattern. An array of color filters is disposed in the spacer pattern.

Fully buried color filter array of image sensor

A pixel cell includes a photodiode disposed in a pixel cell region and proximate to a front side of a semiconductor layer to generate image charge in response to incident light directed through a backside to the photodiode. A cell deep trench isolation (CDTI) structure is disposed in the pixel cell region along an optical path of the incident light to the photodiode and proximate to the backside. The CDTI structure includes a central portion extending a first depth from the backside towards the front side. Planar outer portions extend laterally outward from the central portion. The planar output portions further extend a second depth from the backside towards the front side. The first depth is greater than the second depth. Planes formed by each of the planar outer portions intersect in a line coincident with a longitudinal center line of the central portion of the CDTI structure.

Cell deep trench isolation structure for near infrared improvement

An image sensor includes one or more photodiodes disposed in a semiconductor material to receive image light and generate image charge, and a floating diffusion to receive the image charge from the one or more photodiodes. One or more transfer transistors is coupled to transfer image charge in the one or more photodiodes to the floating diffusion, and a source follower transistor is coupled to amplify the image charge in the floating diffusion. The source follower includes a gate electrode (coupled to the floating diffusion), source and drain electrodes, and an active region disposed in the semiconductor material between the source and drain electrodes. A dielectric material is disposed between the gate electrode and the active region and has a first thickness and a second thickness. The second thickness is greater than the first thickness, and the second thickness is disposed closer to the drain electrode than the first thickness.

Image sensor having a source follower transistor with a multi-thickness gate dielectric

Light control for improved near infrared sensitivity and channel separation for an image sensor. In one embodiment, an image sensor includes: a plurality of photodiodes arranged in rows and columns of a pixel array; and a light filter layer having a plurality of light filters configured over the plurality of photodiodes. The light filter layer has a first side facing the plurality of photodiodes and a second side facing away from the first side. The image sensor also includes a color filter layer having a plurality of color filters configured over the plurality of photodiodes. The color filter layer has a first surface facing the second side of the light filter layer and a second surface facing away from the first layer. Individual micro-lenses are configured to direct incoming light through corresponding light filter and color filter onto the respective photodiode.

Light control for improved near infrared sensitivity and channel separation

An image sensor comprises a semiconductor material having an illuminated surface and a non-illuminated surface; a photodiode formed in the semiconductor material extending from the illuminated surface to receive an incident light through the illuminated surface, wherein the received incident light generates charges in the photodiode; a transfer gate electrically coupled to the photodiode to transfer the generated charges from the photodiode in response to a transfer signal; a floating diffusion electrically coupled to the transfer gate to receive the transferred charges from the photodiode; and a near infrared (NIR) quantum efficiency (QE) and modulation transfer function(MTF) enhancement structure. The NIR QE and MTF enhancement structure comprises: a NIR QE enhancement sub-structure comprising at least one NIR QE enhancement elements within a photosensitive region of the photodiode, wherein the NIR QE enhancement sub-structure is configured to modify the incident light at the illuminated surface of the semiconductor material by at least one of diffraction, deflection and reflection, to redistribute the incident light within the photodiode to improve optical sensitivity, including NIR light sensitivity, of the image sensor; and a MTF enhancement sub-structure disposed on the non-illuminated surface of the semiconductor material, facing toward the NIR QE enhancement sub-structure, wherein the MTF enhancement structure has a geometry corresponding to the NIR QE enhancement sub-structure, to ensure the incident light is still within the photodiode after redistribution.

CMOS image sensor having enhanced near infrared quantum efficiency and modulation transfer function

An image sensor includes a semiconductor material having a front side and a back side opposite the front side. The image sensor also includes a shallow trench isolation (STI) structure, an interlayer dielectric, an intermetal dielectric, and a contact area. The STI structure extends from the front side of the semiconductor material into the semiconductor material. The interlayer dielectric is disposed between the front side of the semiconductor material and the intermetal dielectric. The contact area is disposed proximate to a lateral edge of the semiconductor material. The contact area includes a metal interconnect disposed within the intermetal dielectric and a plurality of contact plugs at least partially disposed within the interlayer dielectric. The contact area also includes a contact pad. The plurality of contact plugs is coupled between the contact pad and the metal interconnect.

Backside illuminated image sensor with improved contact area

An image sensor comprises a semiconductor material having an illuminated surface and a non-illuminated surface; a photodiode formed in the semiconductor material extending from the illuminated surface to receive an incident light through the illuminated surface, wherein the received incident light generates charges in the photodiode; a transfer gate electrically coupled to the photodiode to transfer the generated charges from the photodiode in response to a transfer signal; a floating diffusion electrically coupled to the transfer gate to receive the transferred charges from the photodiode; a near infrared (NIR) quantum efficiency (QE) enhancement structure comprising at least two NIR QE enhancement elements within a region of the photodiode, wherein the NIR QE enhancement structure is configured to modify the incident light at the illuminated surface of the semiconductor material by at least one of diffraction, deflection and reflection, to redistribute the incident light within the photodiode to improve an optical sensitivity, including near-infrared light sensitivity, of the image sensor.

CMOS image sensor having enhanced near infrared quantum efficiency

An image sensor includes a semiconductor material with a photodiode disposed in the semiconductor material. The image sensor also includes a transfer gate electrically coupled to the photodiode to extract image charge from the photodiode in response to a transfer signal. A floating diffusion is electrically coupled to the transfer gate to receive the image charge from the photodiode. At least one isolation structure is disposed in the photodiode, and the at least one isolation structure extends from a surface of the semiconductor material into the photodiode.

Isolation structure in photodiode

An image sensor pixel includes a photosensitive element, a floating diffusion region, a transfer gate, a dielectric charge trapping region, and a first metal contact. The photosensitive element is disposed in a semiconductor layer to receive electromagnetic radiation along a vertical axis. The floating diffusion region is disposed in the semiconductor layer, while the transfer gate is disposed on the semiconductor layer to control a flow of charge produced in the photosensitive element to the floating diffusion region. The dielectric charge trapping device is disposed on the semiconductor layer to receive electromagnetic radiation along the vertical axis and to trap charges in response thereto. The dielectric charge trapping device is further configured to induce charge in the photosensitive element in response to the trapped charges. The first metal contact is coupled to the dielectric charge trapping device to provide a first bias voltage to the dielectric charge trapping device.

Image sensor with dielectric charge trapping device

An integrated circuit system includes a first device wafer bonded to a second device wafer at a bonding interface of dielectrics. Each wafer includes a plurality of dies, where each die includes a device, a metal stack, and a seal ring that is formed at an edge region of the die. Seal rings included in dies of the second device wafer each include a first conductive path provided with metal formed in a first opening that extends from a backside of the second device wafer, through the second device wafer, and through the bonding interface to the seal ring of a corresponding die in the first device wafer.

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Milpitas, CA, United States of America

Cunyu Yang