Beken Corporation

Cunpeng Zhang

Jiazhou Liu

Desheng Hu

An ADC circuit is provided. The ADC circuit may include an array of bit capacitors; a comparator electrically connected to the bit capacitors; a NOR gate electrically connected to the comparator; an AND gate to create an asynchronous clock (ACLK) based on a digital output from the NOR and a synchronous clock (CLKin); a delay control circuit to receive the asynchronous clock and to create a delayed asynchronous clock (ACLKd); and a SAR control circuit to receive a digital output from an output end of the comparator, to receive the delayed asynchronous clock, to transmit a bit control signal (B&#x3c;9:1&#x3e;) to the bit capacitors, and to transmit a delay control word (DL&#x3c;7:1&#x3e;) to the delay control circuit. The ADC circuit can create an asynchronous comparator clock (CKcmp) with a maximum delay value (Td_max), thus leading to an improved conversion linearity and a reduced power consumption.

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Shanghai, China

Cunpeng Zhang