International Business Machines Corporation

Globalfoundries Inc.

Cung D Tran

Emre Alptekin

Viraj Yashawant Sardesai

Reinaldo Ariel Vega

Sameer Hemchand Jain

Ahmet Serkan Ozcan

Huilong Zhu

Bin Yang

Rajasekhar Venigalla

Kathryn Turner Schonenberg

Ravi Prakash Srivastava

Rui Chen

Jian Yu

Xintuo Dai

Sanggil Bae

Dongyue Yang

Minghao Tang

Dong-Ick Lee

Jeffery Burton Maxson

Md Motasim Bellah

Pavan Kumar Chinthamanipeta Sripadarao

Bradley Morgenfeld

Christian J Ayala

Kripa Nidhan Chauhan

Huaxiang Li

Sivananda K Kanakasabapathy

Christian Lavoie

Richard Stephan Wise

Ravikumar Ramachandran

Zhengwen O Li

Unoh Kwon

Henry K Utomo

Hari V Mallela

Mark V Raymond

Gregory Allen Northrop

Domingo A Ferrer

Raghu Mangu

Ayse M Ozbek

In an exemplary method, a first layer is formed on a substrate. First overlay marks are formed in a first zone of the first layer. A non-transparent layer is formed on top of the first layer. At least a portion of the non-transparent layer is removed from an area above the first zone of the first layer. This provides optical access to the first overlay marks. A second layer is formed on top of the non-transparent layer. Second overlay marks are formed in a second zone of the second layer. Position information is obtained from each of the first overlay marks and the second overlay marks.

Structure and method to improve overlay performance in semiconductor devices

Embodiments of present disclosure provide methods of forming a resistor. One such method can include forming a first transistor structure and a second transistor structure on a semiconductor substrate, wherein the first transistor structure includes a dummy gate thereon; forming a mask on the first transistor structure; forming a metal gate on the second transistor structure; removing the mask, after the forming of the metal gate, to expose the first transistor structure; and siliciding a top portion of the dummy gate of the first transistor structure to yield a resistor.

Formation of metal resistor and e-fuse

A method of forming an electrical contact in an integrated circuit, and an integrated circuit are disclosed. In an embodiment, the integrated circuit comprises a substrate, an insulating layer, and a metal layer. An opening is formed through the insulating layer to expose an active area of the substrate. The metal layer forms a cusp at a top end of the opening, narrowing this end of the opening. In embodiments, the method comprises depositing a conductive layer in the opening to form a liner, applying a filler material inside the opening to protect a portion of the liner, removing the cusp to widen the top of the opening while the filler material protects the portion of the liner covered by this material, removing the filler material from the opening, re-lining the opening, and filling the opening with a conductive material to form a contact through the insulating layer.

Contact fill in an integrated circuit

After formation of gate structures over semiconductor fins and prior to formation of raised active regions, a directional ion beam is employed to form a dielectric material portion on end walls of semiconductor fins that are perpendicular to the lengthwise direction of the semiconductor fins. The angle of the directional ion beam is selected to be with a vertical plane including the lengthwise direction of the semiconductor fins, thereby avoiding formation of the dielectric material portion on lengthwise sidewalls of the semiconductor fins. Selective epitaxy of semiconductor material is performed to grow raised active regions from sidewall surfaces of the semiconductor fins. Optionally, horizontal portions of the dielectric material portion may be removed prior to the selective epitaxy process. Further, the dielectric material portion may optionally be removed after the selective epitaxy process.

Fin end spacer for preventing merger of raised active regions

A device is created by forming a layer of dielectric material on a silicon-containing region of a semiconductor substrate. An opening is created through the layer of dielectric material, the opening having a bottom and exposing the silicon-containing region. A metal stack is formed within the opening. The metal stack includes at least a first metal film on the silicon-containing region and a second gettering metal film on the first metal film. The metal stack is annealed to cause oxygen to migrate from the substrate to the gettering metal film. A first liner is formed within the opening. A fill metal is deposited in the opening.

Diffusion-controlled oxygen depletion of semiconductor contact interface

Embodiments of the present invention provide structures and methods for heat suppression in finFET devices. Fins are formed in a semiconductor substrate. A graphene layer is formed on a lower portion of the sidewalls of the fins. A shallow trench isolation region is disposed on the structure and covers the graphene layer, while an upper portion of the fins protrudes from the shallow trench isolation region. The graphene layer may also be deposited on a top surface of the base semiconductor substrate. The graphene serves to conduct heat away from the fins more effectively than other dielectric materials.

Method and structure to suppress finFET heating

A semiconductor device includes a trench region in an interconnect level dielectric layer. A silicide layer is on the bottom of the trench region. Opposing minor sides of the trench region include a spacer layer, but the central portion of the trench region is substantially free from the spacer layer. The spacer layer is formed using an angled gas cluster ion beam.

Unidirectional spacer in trench silicide

A method of forming a trench in an oxide layer; where the oxide layer is formed on top of a nitride layer. The trench is formed using an iterative etching technique until the nitride layer is exposed, each iterative etching step includes; using an isotropic etching technique to remove a portion of the oxide layer, the isotropic etching technique produces a byproduct that remains along a sidewall and a bottom of the trench, then using an anisotropic etching technique to remove the salt from the bottom of the trench, leaving salt on the sidewalls of the trench.

Directional chemical oxide etch technique

Method and structure to suppress FinFET heating

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Niskayuna, NY, United States of America

Cung D Tran