Digital Equipment Corporation

Other

Cuneyt M Ozveren

Robert J Simcoe

Gregory M Waters

Robert J Walsh

Hallam G Murray, Jr

George M Varghese

Greg Waters

A flow control system is disclosed, for a transmitting node and a receiving node. The transmitting node and the receiving node are linked together through multiple connections or virtual circuits. A flow control circuit in the transmitting node limits the number of data transmission units transmitted from the transmitting station, and not yet copied out of the receive buffers in the receiving node, to the total number of receive buffers in the receiving node. The flow control circuit in the transmitting node further controls the transmission of data transmission units on the multiple connections fairly, such that all connections are provided a proportional amount of the total available receive buffers in the receiving node. In an example embodiment, a global counter is used to maintain the total number of receive buffers containing data in the receiving node, and a global limit register contains the maximum number of receive buffers containing data in the receiving node allowed for a single connection. The flow control circuit further includes logic providing fair and efficient allocation of receive buffers across all virtual circuits between a transmitting node and a destination node. The flow control circuit ensures that during steady state operation, receive buffers in the receiving node, which are used to store data transmission units received from the transmitting node, are fairly divided among all active virtual circuits in the transmitting node.

Flow control with smooth limit setting for multiple virtual circuits

In the present invention, one of the bits in the tag value in the cache is hard-wired, for example, to 0, at such a position in the cache that that bit is always set to 0 when a tag is stored in the cache (or forced to 0 when a tag is read from the cache). Instructions executed by the processor can specify a read outside the cache, i.e. of the most recent data written to the main memory by some DMA agent, by specifying a read address with the designated bit equal to one. In this way, a cache miss is forced, allowing the processor to read the most recent data from the main memory of the system and to cache the data. As the cache is refilled from the main memory, the hard-wired tag bit of course remains set to zero. So later processor instructions that read data within the same cache refill block would use the normal address of that data (having the designated bit set to zero). These subsequent reads will not force a cache miss. Instructions executed by the processor can flush the cache by reading a sequence of addresses in which the designated tag bit is one. Since the designated bit is 0 in all cache tags, there will be misses on all words, so the entire cache will be filled from the main memory.

Method and apparatus for efficient cache refilling by the use of forced

The distributed computation of max-min fair rates in general require lookups for all connections. This present method includes a distributed process for computing max-min fair rates in response to a rate allocation request by any connection. The method computes the optimal rate by performing a single lookup of the state for a particular connection. The discrepancies due to omitting the lookup for other connections are corrected when those connections request a rate allocation.

Efficient distributed method for computing max-min fair rates of a

A flow control system is disclosed, for a transmitting node and a receiving node. The transmitting node and the receiving node are linked together through multiple connections or virtual circuits over a communications link. A flow control circuit in the transmitting node limits the amount of bandwidth used over each individual connection, and over all of the connections combined. In an example embodiment, a global counter is used to maintain the total amount of bandwidth consumed overall during a predetermined time period, and a global limit register limits the maximum amount of bandwidth allowed consumed by any single connection during the time period. When the global counter exceeds an upper threshold value, the global limit register is set to a minimum value representing the minimum amount of bandwidth guaranteed to each connection during the time period. If a connection transmits an amount of bandwidth greater than or equal to the value in the global limit register, further transmissions on that connection are disabled for the remainder of the current time period.

Method and apparatus for rate based flow control

A flow control system is disclosed, for a transmitting node and a receiving node. The transmitting node and the receiving node are linked together through multiple connections or virtual circuits. The receiving node includes a connection specific pool of buffers for receiving data transmission units from the transmitting node over each specific connection, and a common pool of buffers for storing data transmission units received from the transmitting node over any of the connections between the transmitting node and the receiving node. A flow control circuit in the transmitting node limits the number of data transmission units transmitted from the transmitting station, and not yet copied out of the receive buffers in the receiving node, to the total number of receive buffers in the receiving node. The flow control circuit in the transmitting node further controls the transmission of data transmission units on the multiple connections fairly, such that all connections are provided a proportional amount of the total available receive buffers in the receiving node. In an example embodiment, a global counter is used to maintain the total number of receive buffers containing data in the receiving node, and a global limit register contains the maximum number of receive buffers containing data in the receiving node allowed for a single connection.

Flow control method and apparatus for systems with long distance links

A method of scheduling a conversation between a designated transmitter adapter card and a designated receiver adapter card, comprising the steps of selecting a first slot having a free channel, selecting a second slot having the designated transmitter adapter card free, selecting a third slot having the designated receiver adapter card free, assigning a connection between the designated transmitter adapter card and the designated receiver adapter card in the free channel in the first slot, resolving any conflict between the designated transmitter adapter card and any other conversation by swapping conversations between the first slot and the second slot, resolving any conflict between the designated receiver adapter card and any other conversation by swapping conversations between the first slot and the third slot.

Growing community of inventors

Somerville, MA, United States of America

Cuneyt M Ozveren