Stmicroelectronics S.r.l.

Bull Hn Information Systems Italia S.p.a.

Stmicroelectronics (grenoble) Sas

Cristina Silvano

Danilo Pietro Pau

Marcello Coppola

Riccardo Locatelli

Valerio Catalano

Roberto Zafalon

Vittorio Zaccaria

Mariagiovanna Sami

Donatella Sciuto

Gianluca Palermo

Leandro Fiorin

A data protection device for an interconnect network on chip (NoC) includes a header encoder that receives input requests for generating network packets. The encoder routes the input requests to a destination address. An access control unit controls and allows access to the destination address. The access control unit uses a memory to store access rules for controlling access to the network as a function of the destination address and of a source of the input request.

Programmable data protection device, secure programming manager system and process for controlling access to an interconnect network for an integrated circuit

An architecture for a pipeline processor circuit, preferably of the VLIW type, comprises a plurality of stages and a network of forwarding paths which connect pairs of said stages, as well as a register file for operand write-back. An optimization-of-power-consumption function is provided via inhibition of writing and subsequent readings in said register file of operands retrievable from said forwarding network on account of their reduced liveness length.

Processor architecture

Digital information error correcting apparatus for the correction of single errors (SEC), the detection of double errors (DED) and multiple single byte errors (SBD) and the correction of an odd number of single byte errors (ODDSBC) comprising a syndrome generator with generation matrices constituted by the juxtaposition of a plurality of non-zero and distinct submatrices having b rows and r columns where b is the number of bits per byte and r (r.gtoreq.b+2) is the number of syndrome and error check bits, each constituted by an identity submatrix Ib having b rows and columns, vertically aligned over a matrix H having r-b rows and b columns formed by an even number .gtoreq.2 of rows of all 1 elements and the remaining rows being all 0 elements.

Digital information error correcting apparatus for single error

Growing community of inventors

Milan, Italy

Cristina Silvano