Intel Corporation

Universidad Politècnica De València

Crispin Gomez Requena

Fernando Latorre

Grigorios Magklis

Pedro Lopez

Marc Lupon

Pedro Marcuello

Polychronis Xekalakis

Raul Martinez

Josep M Codina

Enric Gibert Codina

Daniel Ortega

Kyriakos A Stavrou

Demos Pavlou

Georgios Tournavitis

Mirem Hyuseinova

Christos E Kotselidis

Antonio Gonzalez

Carlos Madriles

Alejandro Martinez Vicente

Alejandro Vicente Martinez

Carlos Madriles Gimeno

Marti Torrents Lapuerta

Jose Francisco Duato Marin

Francisco Gilabert Villamon

Maria Engracia Gomez Requena

Pedro Juan Lopez Rodriguez

Antonio Gonzelez

A computer-readable storage medium, method and system for optimization-level aware branch prediction is described. A gear level is assigned to a set of application instructions that have been optimized. The gear level is also stored in a register of a branch prediction unit of a processor. Branch prediction is then performed by the processor based upon the gear level.

Instruction and logic for optimization level aware branch prediction

A combination of hardware and software collect profile data for asynchronous events, at code region granularity. An exemplary embodiment is directed to collecting metrics for prefetching events, which are asynchronous in nature. Instructions that belong to a code region are identified using one of several alternative techniques, causing a profile bit to be set for the instruction, as a marker. Each line of a data block that is prefetched is similarly marked. Events corresponding to the profile data being collected and resulting from instructions within the code region are then identified. Each time that one of the different types of events is identified, a corresponding counter is incremented. Following execution of the instructions within the code region, the profile data accumulated in the counters are collected, and the counters are reset for use with a new code region.

Propagating a prefetching profile bit from a prefetch queue to a data cache to indicate that a line was prefetched in response to an instruction within a code region

Disclosed is an apparatus and method to manage instruction cache prefetching from an instruction cache. A processor may comprise: a prefetch engine; a branch prediction engine to predict the outcome of a branch; and dynamic optimizer. The dynamic optimizer may be used to control: identifying common instruction cache misses and inserting a prefetch instruction from the prefetch engine to the instruction cache.

Managed instruction cache prefetching

The invention falls within the technology of multistage interconnection network such as fat-trees, comprising at least one switch located at a stage (s) and configured to send, through an output port from a number (k) of output ports forming an ordered list, at least a data packet containing a destination address identified by a n-tuple with a plurality (n) of components (p, . . . , p, p), and s&#x3b5;{0 . . . (n&#x2212;1)}. The invention has application for both source and distributed routing, as deterministic and as adaptive routing, selecting an output port to be the unique or the default option to forward the packets at the switch which is the output port that has a position in the ordered list of output ports corresponding to the component (p) of the destination address at the position given by the stage (s) of the switch.

Method and switch for routing data packets in interconnection networks

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Valencia, Spain

Crispin Gomez Requena