Vlsi Technology, Inc.

Creighton S Asato

Christoph Ditzen

Suresh K Dholakia

N-input Logic Gates are presented that have a high speed transmission path for a first input logic signal A.sub.1. For an AND Gate embodiment, a logic signal A.sub.1 is applied to an input of a master transmission gate that is transmitting if all of logic signals A.sub.2, . . . , A.sub.N are logic one signals and is otherwise nontransmitting. For an OR Gate embodiment, a logic signal A.sub.1 is applied to an input of a master transmission gate that is transmitting if all of logic signals A.sub.2, . . . , A.sub.N are logic zero signals and is otherwise nontransmitting.

Fast logic circuits

According to a method for designating the locations of pipelining stages in multi-stage datapath elements, the delay associated with each stage of the multi-stage element is estimated. Then, beginning with a designated stage of the multi-stage element, the estimated delays for the individual stages are added to obtain an accumulated delay time. Whenever the accumulated delay time exceeds a desired cycle time, a pipelining stage is inserted into the multi-stage element prior to the stage which caused the accumulated delay time to exceed the desired operating cycle time. Then, the method is continued for succeeding stages in the datapath element until all of its stages have been accounted for.

Technique for placement of pipelining stages in multi-stage datapath

A conditional-sum carry structure has an architecture which is sufficiently regular that the structure can be conveniently generated by an automated compiler. The carry structure includes a column of input cells, each of the cells in the column being operative for receiving binary numbers and, for each of the received numbers, generating a sum bit and two carry-out bits. Further the carry structure includes an array of columns of binary logic elements comprised of dual multiplexers (MUX MUX elements), dual exclusive OR gates (XOR XOR elements), multiplexer and exclusive OR gate circuits (MUX XOR elements) and multiplexer units (ONE MUX elements) for receiving sum bits and carry-out bits from the input cells and for performing the operations of a conditional-sum carry structure.

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Sunnyvale, CA, United States of America

Creighton S Asato