Analog Devices,inc.

Craig Wilson

Derek F Bowers

Gregory Keith Cestra

Michael Thomas Dunbar

Michael Lee

Steven Wright

Philip Judge

A thin film composition is made from silicon, an insulator such as alumina or silicon dioxide, and at least one additional material such as chromium, nickel, boron and/or carbon. These materials are combined to provide a thin film having a &#x3c1; of at least 0.02 &#x3a9;-cm (typically 0.02-1.0 &#x3a9;-cm), and a TCR of less than &#xb1;1000 ppm/&#xb0; C. (typically less than &#xb1;300 ppm/&#xb0; C.). A sheet resistance of at least 20 k&#x3a9;/&#x25a1; may also be obtained. The resulting thin film is preferably at least 200thick, to reduce surface scattering conduction currents.

High resistivity thin film composition and fabrication method

A layered capacitor structure comprises two or more semiconductor/dielectric plates formed above an insulating surface which provides mechanical support, with the plates arranged in a vertical stack on the insulating surface. An insulating layer is on each plate, patterned and etched to provide an opening which allows the top of one plate to be in physical and electrical contact with the bottom of the subsequent plate. Contact openings are provided through the insulating layers, each of which provides access to a respective semiconductor layer and is insulated from any other semiconductor/dielectric plate. Electrical contacts through the contact openings provide electrical connections to respective semiconductor layers. The present structure can include as many stacked layers as needed to provide a desired total capacitance or range of capacitances.

Layered capacitor architecture and fabrication method

The present invention provides a JFET which receives an additional implant during fabrication, which extends its drain region towards its source region, and/or its source region towards its drain region. The implant reduces the magnitude of the e-field that would otherwise arise at the drain/channel (and/or source/channel) junction for a given drain and/or source voltage, thereby reducing the severity of the gate current and breakdown problems associated with the e-field. The JFET's gate layer is preferably sized to have a width which provides respective gaps between the gate layer's lateral boundaries and the drain and/or source regions for each implant, with each implant implanted in a respective gap.

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Livermore, CA, United States of America

Craig Wilson