Silicon Aquarius, Inc.

Craig Waller

Wayland Bart Holland

G R Mohan Rao

Jason Stevens

Gary Johnson

A content addressable memory cell includes a first storage element for storing information and a first transistor for selectively transferring charge representing information from a first bitline to the first storage element A second transistor selectively transfers charge representing information from a second bitline to a second storage element First and second comparelines carry first and second bits of a comparand to a comparator which compares the first and second bits of the comparand with information stored on the first and second storage elements. In response, comparator selectively controls a voltage on a corresponding one of a plurality of matchline

Content addressable memory cells and systems and devices using the same

A content addressable memory cell,includes a first storage element,for storing information and a first transistor,for selectively transferring charge representing information from a first bitline,to the first storage element,A second transistor,selectively transfers charge representing information from a second bitline,to a second storage element,First and second comparelines,carry first and second bits of a comparand to a comparator,which compares the first and second bits of the comparand with information stored on the first and second storage elements. In response, comparator,selectively controls a voltage on a corresponding one of a plurality of matchline

A memory,including an array of rows and columns of memory cells,is disclosed. For each column, first and second interdigitated bitlines,are coupled to the cells of the column. The first bitlines,has an end coupled to a sense amplifier,at a first boundary of the array and a second bitline,has an end coupled to a second sense amplifier at a second boundary of the array, the first and second boundaries being spaced apart by the array. Control circuitry,precharges the first bitlines,of the columns of the array substantially simultaneous to an access to the array through the second bitlines,of selected columns of the array.

Arrays of two-transistor, one-capacitor dynamic random access memory cells with interdigitated bitlines

A dynamic random access memory,includes an array,of physical rows and columns of memory cells, the cells of each row coupled to first and second wordlines,and first and second bitlines,A direct input/output data path,having a width equal to a width of the rows supports simultaneous writing to each of the cells along a selected row using the first wordlines and first bitlines during a single access cycle without restore.

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Garland, TX, United States of America

Craig Waller