John Fluke Mfg. Co., Inc.

Other

Craig Vincent Johnson

Henriecus Koeman

John D Polstra

Bruce T White

An efficient method for calculating Power Sum cross-talk loss is provided. Cross-talk loss measurements may include near-end cross-talk (NEXT) loss, far-end cross-talk (FEXT) loss, multiple disturber NEXT (MD NEXT) loss, and multiple disturber FEXT (MD FEXT) loss. Pair-to-Pair cross-talk loss responses are collected between a given wire pair and all the other wire pairs of concern, with each pair-to-pair cross-talk loss measurement having a number of frequency data points corresponding to the frequencies of interest. The pair-to-pair cross-talk loss response having the lowest positive value for a particular frequency data point is first selected as the baseline cross-talk loss response. The effects of each of the remaining pair-to-pair cross-talk loss responses on the baseline cross-talk loss response are then accounted for by applying power sum contribution values obtained from a look-up table. In this way, Estimated Power Sum cross-talk loss may be calculated for each of the corresponding frequency data points from each of the pair-to-pair cross-talk loss measurements in an efficient manner.

Method for efficient calculation of power sum cross-talk loss

An apparatus, method and data structure for validating the data bus of a microprocessor-based unit under test in which bit patterns having half as many bits as the width of the data bus are applied to the data bus along with another bit pattern which is either the complemented or true replication of the bit pattern. Evaluation of the resulting bit patterns on the data bus permits a validation of the entire width of the data bus which, if no faults are reported, obviates not only probing of the data bus by the operator but data bus diagnosis, as well. A particular data structure of a preferred bit pattern sequence avoids any fault on any data line being reported as a pass.

Apparatus, method and data structure for validation of kernel data bus

A method of and system of high-speed, high-accuracy functional testing of memories in microprocessor-based units or boards under test includes a test system that is effectively permanently coupled to the unit under test bus structure during test execution and operates at the unit under test's clock rate. The test program may be stored in the unit under test's own memory, or may be electrically transferred from the test system's memory to the memory under test using a memory overlay technique. Memory testing speed may be further incresed by taking advantage of block move and compare features of newer microprocessors. An algorithm which exploits the block move and compare features is provided.

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Everett, WA, United States of America

Craig Vincent Johnson