Micron Technology Incorporated

Texas Instruments Corporation

T-ram Semiconductor, Inc.

Craig Thomas Salling

Brian W Huber

Zhiqiang (Jeff) Wu

Charvaka Duvvury

Che-Jen Hu

Jerry Che-Jen Hu

Wei-Tsun Shiau

Amitava Chatterjee

Gianluca Boselli

Roger A Cline

Kemal Tamer San

Youngmin Kim

Siak Chon Kee

Pierre Dermy

A protection circuit for protecting an integrated circuit padagainst an ESD pulse, which comprises a discharge circuit having an elongated MOS transistor(preferably pMOS) in a substrate(preferably n-type), said discharge circuit operable to discharge the ESD pulse to the pad, to ground. The embodiment further contains a pump circuit connected to the pad for receiving a portion of the pulse's current; the pump circuit comprises a componentdetermining the size of this current portion (for example, another transistor, a string of forward diodes, or a reverse Zener diode), wherein the component is connected to ground. A discrete resistor(for example about 40 to 60&#x3a9;) is connected between the pad and the component and is operable to generate a voltage drop (about 0.5 to 1.0 V) by the current portion. A plurality of contacts to the substrate connects to the resistor so that the voltage drop is uniformly impressed on the substrate to ensure uniform turn-on of the elongated transistor for uniform pulse discharge.

Body-biased pMOS protection against electrostatic discharge

Depletion-mode ferroelectric transistors are adapted for use as non-volatile memory cells for memory devices and electronic systems. Various embodiments are described having a diode interposed between the bit line and a source/drain region of the transistor for added margin against read disturb.

Junction-isolated depletion mode ferroelectric memory devices and systems

A ground potential is applied to a first word line coupled to a control gate of a selected ferroelectric memory cell in an array of ferroelectric memory cells. A fraction of a programming voltage is applied to other word lines coupled to control gates of non-selected memory cells not associated with the first word line. The programming voltage is applied to a first program line coupled to a first source/drain region of the selected memory cell and to a first bit line coupled to a second source/drain region of the selected memory cell. A fraction of the programming voltage is applied to other program lines coupled to first source/drain regions of non-selected memory cells not associated with the first program line and to other bit lines coupled to second source/drain regions of non-selected memory cells not associated with the first bit line.

Writing to ferroelectric memory devices

An electrostatic discharge protective circuit may comprise a low-pass filter and a high-pass filter to receive and filter signals of a supply line. Control logic may receive output signals of the low-pass and high-pass filters and may operate a gateable channel to shunt current of the supply line dependent on the output signals from the filters.

Electrostatic discharge protection circuit

A programming voltage is applied to a first word line coupled to a control gate of a selected ferroelectric memory cell in an array of ferroelectric memory cells. A gate/source voltage equal to the programming voltage is sufficient to reverse polarity of each memory cell. A ground potential is applied to a first program line coupled to a first source/drain region of the selected memory cell and to a first bit line coupled to a second source/drain region of the selected memory cell. A fraction of the programming voltage is applied to other word lines coupled to control gates of non-selected memory cells not associated with the first word line, other program lines coupled to first source/drain regions of non-selected memory cells not associated with the first program line, and other bit lines coupled to second source/drain regions of non-selected memory cells not associated with the first bit line.

Depletion-mode ferroelectric transistors are adapted for use as non-volatile memory cells. Various embodiments are described having a diode interposed between the bit line and a source/drain region of the transistor for added margin against read disturb. Various additional embodiments are described having an array architecture such that two memory cells sharing the same bit line also share the same program line. Using this configuration, non-selected cells are readily supplied with gate/source voltages sufficient to maintain the cells in a deactivated state during read and write operations on selected cells.

Junction-isolated depletion mode ferroelectric memory devices

Protection circuitry () for protecting an integrated circuit against an ESD pulse is provided. The protection circuitry () includes a discharge circuitry () on a substrate () that discharges an ESD pulse to the integrated circuit to ground (). The protection circuitry () also includes a drive circuitry () that uses a portion of the ESD pulse voltage to bias the substrate () using a first guard ring () in the substrate (), which surrounds the discharge circuitry () and drive circuitry (). The protection circuitry () further includes a second guard ring () in substrate (), which surrounds the first guard ring () and connects to Vss/ground potential (), thereby providing uniformity of the substrate bias.

ESD protection with uniform substrate bias

Depletion mode ferroelectric transistors are adapted for use as non-volatile memory cells. Various embodiments are described having a diode interposed between the bit line and a source/drain region of the transistor for added margin against read disturb. Various additional embodiments are described having an array architecture such that two memory cells sharing the same bit line also share the same program line. Using this configuration, non-selected cells are readily supplied with gate/source voltages sufficient to maintain the cells in a deactivated state during read and write operations on selected cells.

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Plano, TX, United States of America

Craig Thomas Salling