International Business Machines Corporation

Craig T Atherton

Oz Dov Hershkovitz

Olaf Knute Hendrickson

Avishai Moshe Fedida

A method and apparatus are provided for implementing automated memory address recording in constrained random test generation for verification of processor hardware designs. A test generation program includes a built in feature to keep track of storage addresses used and to make the addresses available to the test definition. This built in feature of a constrained random test generator allows storage addresses used in the past to be accessed by the current instruction generation eliminating the requirement of deliberately establishing target addresses first. This allows separate test events to interact with the same storage addresses without having to write a special test.

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Burlington, VT, United States of America

Craig T Atherton