Altera Corporation

Waveone Inc.

Other

Craig S Lytle

Kerry S Veenstra

Francis B Heile

Bruce B Pedersen

Richard G Cliff

Bahram Ahanin

Donald F Faria

Joseph Huang

David Wolk Mendel

Christopher F Lane

Srinivas T Reddy

David Edward Jefferson

L Todd Cope

Rina Raman

Lubomir Dimitrov Bourdev

Sanjay Nair

Alexander Anderson

Hervé Guihot

Brandon Sprague

Kedar Tatwawadi

Jeffrey Fox

Robert R Bielby

Robert Richard Noel Bielby

Oren Rippel

Brad Kadet

Roger Bryner

Ricky W Ho

A compression system trains a machine-learned compression model that includes components for an encoder and decoder. In one embodiment, the compression model is trained to receive parameter information on how a target frame should be encoded with respect to one or more encoding parameters, and encodes the target frame according to the respective values of the encoding parameters for the target frame. In particular, the encoder of the compression model includes at least an encoding system configured to encode a target frame and generate compressed code that can be transmitted by, for example, a sender system to a receiver system. The decoder of the compression model includes a decoding system trained in conjunction with the encoding system. The decoding system is configured to receive the compressed code for the target frame and reconstruct the target frame for the receiver system.

Parameter map for machine-learned video compression

A cloud service system manages a filter repository including filters for encoding and decoding media content (e.g. text, image, audio, video, etc.). The cloud service system may receive a request from a client device to provide a filter for installation on a node such as an endpoint device (e.g. pipeline node). The request includes information such as a type of bitstream to be processed by the requested filter. The request may further include other information such as hardware configuration and functionality attribute. The cloud service system may access the filter repository that stores the plurality of filters including encoder filters and decoder filters and may select a filter that is configured to process the type of bitstream identified in the request and provide the selected filter to the client device.

System for training and deploying filters for encoding and decoding

A compression system trains a compression model for an encoder and decoder. In one embodiment, the compression model includes a machine-learned in-loop flow predictor that generates a flow prediction from previously reconstructed frames. The machine-learned flow predictor is coupled to receive a set of previously reconstructed frames and output a flow prediction for a target frame that is an estimation of the flow for the target frame. In particular, since the flow prediction can be generated by the decoder using the set of previously reconstructed frames, the encoder may transmit a flow delta that indicates a difference between the flow prediction and the actual flow for the target frame, instead of transmitting the flow itself. In this manner, the encoder can transmit a significantly smaller number of bits to the receiver, improving computational efficiency.

Machine-learned in-loop predictor for video compression

Various embodiments provide for a front-pivot, pan-tilt-zoom camera designed to fit into an opening formed in a chain-link fence to enable video recording and photography of activities through the narrow opening in the fence. In some embodiments, the camera can be mounted to the chain-link fence and allow remote operation of the motorized pan and tilt control as well as zoom, focus, exposure and other common camera features. The pan and tilt mechanism pivots the imaging device in the camera around an axis of rotation in front of the imaging device which allows the field of view of the imaging device to be changed while remaining inserted into the fence opening.

Front-pivot, motorized pan-tilt camera

Various embodiments provide for a telescoping monopod or a tripod with a telescoping pole that allows an imaging device to be mounted thereon and be remotely controlled via a mobile device. A mounting assembly on the monopod can include motors that facilitate pan and tilt functionality, and a controller that operates the motors and the imaging device. The controller can control the motors and imaging device based on instruction received wirelessly from a mobile device. A base enclosure in the monopod can include one or more batteries that power the imaging device and mounting assembly and also include memory for digital storage of the images recorded by the imaging device.

Camera integrated with monopad and remote control

A heterogeneous device including multiple types of resources is provided to implement multiple logic functions. Logic functions are provided with multiple configuration options. In one example, an optimal set of configuration options along with a target device are selected using cost and resource availability information associated with multiple heterogeneous programmable chips and the configuration options provided with the logic blocks.

Methods and apparatus for implementing logic functions on a heterogeneous programmable device

Various techniques permit more thorough development of digital systems and devices by designers while protecting the proprietary interests of the owners of the intellectual property incorporated in such systems and devices. More specifically, systems, apparatus, methods and computer program products control use of hardware and software and IP implemented as user logic in a programmed device. The programmed device includes programmed logic that has designed logic and control logic. The designed logic includes user logic and protected logic such as IP cores, the use of which is to be controlled. The control logic includes a signal generator external to the designed logic. This signal generator contains clock means and a timeout circuit. A controller is connected to the programmed device by a tether. The controller periodically sends a keep alive signal via the tether to the signal generator. These keep alive signals may be single bit or multi-bit tokens which are processed in the programmed device by the signal generator. The signal generator disables the programmed device when the signal generator reaches a programmed time limit before receiving a keep alive signal from the controller. Disabling the programmed device can be accomplished by disabling either the user logic or the protected logic or both.

Method and apparatus for controlling evaluation of protected intellectual property in hardware

A programmable logic array integrated circuit device includes a plurality of regions of programmable logic disposed on the device in a two-dimensional array of intersecting rows and columns. Interconnection conductors are associated with each row and column. The interconnection conductors associated with each row include some that extend continuously along the entire length of the row and some that extend continuously along only the left or right half of the row. To increase the flexibility with which the logic regions can be connected to the row and column conductors, adjacent regions are paired and circuitry is provided for allowing the outputs of each pair to be swapped for driving the row and column conductors. Registers in logic regions can still be used for other purposes when not being used to register the main combinatorial outputs of the logic regions. Many other enhanced features are also provided.

Programmable logic array integrated circuit devices

A programmable logic array integrated circuit has a number of programmable logic modules which are grouped together in a plurality of logic array blocks (&ldquo;LABs&rdquo;). The LABs are arranged on the circuit in a two dimensional array. A conductor network is provided for interconnecting any logic module with any other logic module. In addition, adjacent or nearby logic modules are connectable to one another for such special purposes as providing a carry chain between logic modules and/or for connecting two or more modules together to provide more complex logic functions without having to make use of the general interconnection network. Another network of so-called fast or universal conductors is provided for distributing widely used logic signals such as clock and clear signals throughout the circuit. Multiplexers can be used in various ways to reduce the number of programmable interconnections required between signal conductors.

Programmable logic array integrated circuits

A programmable logic device architecture with a highly routable programmable interconnect structure. The arrangement of the logic array blocks (LABs), programmable interconnect structure, and other logical elements forms a Clos network. After specific constraints have been met, the architecture is guaranteed to route. The architecture is provably routable when there is no fan-out in the middle stage. A LAB ( ) comprises an input multiplexer region ( ), logic elements ( ), input-output pins ( ), and output multiplexer region ( ).

Programmable logic device with highly routable interconnect

A programmable logic device integrated circuit incorporating a memory block. The memory block ( ) is a general-purpose memory configurable as a random access memory (RAM) or a first-in first-out (FIFO) memory. In one embodiment, the organization of memory block ( ) may have variable word size and depth size. Memory block ( ) is coupled to a programmable interconnect array ( ). Signals from the programmable interconnect array ( ) may be programmably coupled to the data, address, and control inputs of the memory block. Data output and status flag signals from the memory block are programmably coupled to the programmable interconnect array ( ).

Programmable logic array integrated circuit with general-purpose memory configurable as a random access or FIFO memory

A programmable logic device architecture with a highly routable programmable interconnect structure. The arrangement of the logic array blocks (LABs), programmable interconnect structure, and other logical elements forms a Clos network. After specific constraints have been met, the architecture is guaranteed to route. The architecture is provably routable when there is no fan-out in the middle stage. A LAB (A-,) comprises an input multiplexer region (A-,), logic elements (A-,), input-output pins (A-,), and output multiplexer region (A-,). Furthermore, a logic device and a method of operating a logic device. The device includes logic elements (B-,) that perform desired logic functions and routing functions. The logic elements (B-,) are arranged in larger logic blocks known as logic array blocks (B-,) that have local interconnection systems. The logic array blocks (B-,) are configured to provide global interconnections. The configuration provides a Clos network, whereby a signal may be routed from any input to any output without blocking.

A programmable logic device integrated circuit incorporating a first-in, first-out memory block (,). First-in, first-out memory block (,) is coupled to a programmable interconnect array (,). Signals from the logic array blocks (LABs) (,) are connected to the control inputs of the first-in, first-out memory (,). In one embodiment, the programmable interconnect array (,) may be programmably coupled to the control inputs (,) of the first-in, first-out memory block. Status flag signals (,) from the first-in, first-out memory block (,) are programmably coupled to the programmable interconnect array (,). Data input (,) and data output (,) to first-in, first-out memory block (,) may be coupled to external, off-chip circuitry.

Growing community of inventors

Mountain View, CA, United States of America

Craig S Lytle