Dell USA L P

Other

National Instruments Corporation

Craig S Jones

Kenneth L Jeffries

Terry J Parks

Victor K Pecone

Jonathan W Hearn

Jay R Lory

Jason D Tongen

John J Pearce

Eric R Gardiner

Robert D Ross

Darius D Gaskins

Charles P Zeller

Anthony L Overfield

Jim Walker

Alan Davis

Tony Patterson

A selectively transparent bridge facilitates a PCI device presenting itself to the host as a PCI-to-PCI bridge but selectively hiding and isolating hardware from the host bus. PCI configuration may be achieved through the standard PCI Express configuration mechanisms, but instead of configuring devices directly, a configuration processor in the selectively transparent bridge may intercept the configuration packets from the host, and create a virtual configuration to alter how the bus topology appears to the host. Devices are selectively hidden and managed by the configuration processor, resulting in simplified complexity and bus depth. Since the selectively transparent bridge appears to the host as a transparent bridge, no special drivers or resource preallocations are required, although the selectively transparent bridge fully supports special drivers and/or resource preallocations. Devices located/connected downstream of the bridge may therefore function with unmodified drivers.

Selectively transparent bridge for peripheral component interconnect express bus system

A host system may couple to a PCIe subsystem. During setup of the PCIe subsystem, the BIOS in the host system may first be informed that the devices to be coupled are not PCIe devices, and certain amount of memory is required for these devices. The BIOS may therefore not attempt to configure the devices, and may instead allocate the required memory space. When the operating system boots up, it may not attempt to configure the devices, loading a custom driver instead of an existing PCI driver to configure the bus. Once loaded, the custom driver may configure the devices, then inform the OS that there are PCIe devices in the system at the specified addresses, which may cause the OS to load and execute existing PCIe device drivers to operate/use the devices. The proprietary driver may also be used to handle traffic between the PCIe drivers and the OS.

Opaque bridge for peripheral component interconnect express bus systems

Smart bridge and use. The smart bridge includes a functional unit, memory, and a switch for routing data between a host and multiple devices using a routing table. The bridge stores a forwarding address range (FAR) as a bridge representation of hardware memory resources required by the devices. The FAR is an integer multiple of a first specified minimum size and is aligned with the first specified minimum size. The bridge representation is converted to an endpoint representation that includes multiple virtual memory resources based on a starting address of the FAR. Each virtual memory resource has a respective sub-address range with a size that is a power of 2 multiple of a second specified minimum size, which is less than the first specified minimum size, and is aligned accordingly. The endpoint representation is usable by the switch or the host to allocate the virtual memory resources to the devices.

Address range decomposition

A mapping and correspondence may be established between a virtual topology and a physical topology of a PCIe subsystem, and a host may be presented with the virtual topology but not the actual physical topology. A semi transparent bridge may couple an upstream host to the PCIe subsystem that includes intermediary bridges and respective PCIe endpoints coupled downstream from the intermediary bridges. The intermediary bridges may be hidden from the host, while the respective PCIe endpoints may be visible to the host. A configuration block may provide to the upstream host, during a setup mode, first memory allocation information corresponding to the intermediary switches, responsive to the upstream host expecting second memory allocation information corresponding to the respective PCIe endpoints. The configuration block may then provide to the upstream host, during a runtime mode, the second memory allocation information, responsive to the upstream host expecting the second memory allocation information.

Hidden base address register programming in peripheral component interconnect express buses

Selectively transparent bridge for peripheral component interconnect express bus systems

A combination clip and table top supporting device for use with any of a smartphone or other portable electronic device. The device includes a body having opposing and extending ends and which is constructed of a resilient and biasing material. The attachable electronic device is adapted to secure to a face of the body. A multi-sided kickstand is pivotally attached to the body and adjustable for supporting the body and attached device upon a surface location.

Affixable belt clip for a phone incorporating an adjustable kickstand

A rotary engine assembly having a three dimensional and substantially cylindrical shaped outer casing. A plurality of pistons are mounted in circumferentially traversable fashion within the casing, each including a male feature extending from one end and a recess defined within an opposing piston end and within which the male feature seats at selected stages during a rotary combustion cycle associated with the pistons. A valve is operable with each of the pistons and in order to communicate, to the associated piston, at least one air intake port and exhaust port extending through the casings and communicable with the pistons during discrete stages of the combustion cycle. A plurality of ratchet plates are operably engaged to the pistons and traversable therewith, the ratchet plates engaging and actuating in rotary fashion a central crankshaft. An oil feed line is associated with a central location of the engine assembly, the oil being disbursed through centrifugal force throughout the pistons and associated contact surfaces and recollecting in gravity fashion within a lowermost disposed oil pan.

Rotary and centrifugal driven internal combustion engine

A drag-reduction system incorporated within an inwardly stepped underside of a boat hull for reducing a degree of water pressure forces exerted upon the boat hull during travel of the boat upon a body of water. A plurality of spaced apart rollers are secured at a generally aft location of the boat hull associated with the inwardly stepped underside and extend in parallel spaced apart fashion and perpendicularly to a longitudinal water flow across the boat hull experienced during propulsion of the hull. An elongate and planar shaped belt of a water impervious material having an established width and defining a continuous extending and closed loop is mounted over the plurality of spaced apart rollers. A first linearly extending location of the continuous belt is recessed within the stepped underside of the hull and a second linearly extending location is in contact with the longitudinal water flow. The second linearly extending location of the belt is capable of being translated in a direction consistent with the longitudinal water flow across the boat hull. A single drive roller or pair of drive rollers associated with the plurality of spaced apart rollers is capable of driving the belt at a velocity equal to or greater than a velocity of the longitudinal water flow traveling along the boat hull.

Drag reduction assembly for use with a boat hull

A tile for superposition over a horizontal floor comprises a thin flat metal plate of uniform thickness with a plurality of apertures extending laterally therethrough in spaced relation to one another and to the edges of thereof and having a non-metallic insert in each of the apertures of a thickness less than the thickness of the metal portion of the tile and having an upper surface disposed below the upper surface of the metal portion of the tile.

Decorative anti slip floor covering

A system and method for reducing latency in systems using layered device driver architectures. The preferred embodiment of the invention comprises a disk subsystem including a layered device driver architecture which performs various RAID operations. A plurality of the driver layers are defined to use a common request structure. The system and method of the present invention determines if a request maps unmodified to a lower driver layer and 'quick launches' these requests to the lower driver layer according to the present invention. When a host request is received, the first layer device driver executing on the disk controller determines if the enqueued request is atomic, i.e., if the request maps unmodified to the next lower level driver layer. If so, then the request is dequeued from the first level queue and enqueued on the next lower level layer queue, avoiding steps of allocating and populating a new request structure for the lower level driver. This process preferably repeats for each of the device driver layers. When the last device driver layer completes, each device driver performs a completion callback to its calling driver layer. If a respective device driver layer was quick launched from a higher level driver layer, bypassing one or more intermediate driver layers, then the respective device driver layer performs a completion callback to the higher level driver layer, also bypassing the intermediate layers. Therefore, the system and method of the present invention reduces and/or virtually eliminates added latency in layered device driver architectures for those requests which pass through one or more device driver layers unmodified.

System and method for reducing latency in layered device driver

A disk controller for a disk drive array which maintains two representations of all drive defects. The controller maintains a logical defect list that is used to maintain the sector remapping structure when reconstructing redundancy information. The controller also maintains a physical defect list that is used to preserve known defect information on a physical disk basis. The physical defect list stores the defects even if the logical configuration of the disks changes. When the controller of the present invention determines that a block of data is bad, the controller allocates space for the respective stripe in an alternate block, recovers the data in the stripe and writes the recovered data to the newly allocated stripe. The controller then updates the remap tables in memory with the remap information. On each disk access, the controller searches the logical defect list to determine if the access involves one or more bad blocks. When a failed disk is replaced, the controller rebuilds the data from the failed drive using the remaining data and parity. The controller also uses both the logical and physical defect lists to unmap remapped sectors which were originally remapped due to defective sectors on the replaced disk drive.

Method and controller for defect tracking in a redundant array

A computer system including a host CPU, a primary PCI bus coupled to the CPU, and a bus adapter coupled to the primary PCI bus, wherein the host CPU can access peripherals comprised in the bus adapter even when the bus adapter is inoperable. The bus adapter includes a PCI to PCI interface controller which includes a primary PCI interface for coupling to the primary PCI bus and a secondary PCI interface bridge for coupling to a secondary PCI bus. Peripheral bus interface logic is coupled between the primary PCI interface and the secondary PCI interface, and this interface logic couples to various peripheral devices, including ROM/Flash memory and non-volatile static random access memory (NVSRAM). According to the present invention, a host utility executing on the CPU can access the peripheral devices without having to access the secondary PCI bus. Thus, if the secondary PCI bus becomes inoperable or the local processor is unable to boot the host can still access the memory in the peripheral devices because the peripheral interface is effectively decoupled from the secondary PCI bus and the local processor. The present invention includes a host utility which can update the Flash memory, thereby providing a cost-effective and efficient mechanism for restoring code in a corrupted Flash device on a failed board. This also enables the Flash memory to be programmed for the first time during manufacturing. The system and method of the present invention allows the host CPU to access the NVRAM to obtain event failure information even if the secondary PCI bus has failed.

System and method for accessing peripheral devices on a non-functional

A relatively permanent and indestructible covering (10) utilizes a plurality of single ply tiles (12) which are bonded to a base floor surface (14) and provided with a protective coating in a single step by applying at least one protective bonding coating, such as an epoxy coating, over the top of plurality of tiles. To facilitate bonding to base floor surface, each of the plurality of tiles (12) are formed with a plurality of holes passing through the surface thereof. A color finish coating can also be provided over the top of the array of tiles by utilizing a protective bonding coating having a paint or paint-like quality. In a preferred embodiment, the tiles (12) are formed from a metal such as aluminum.

Finish floor covering utilizing single ply tiles

An essential utility routine accesses a protected computer system component by making a call to a coprocessor that performs a desired function to avoid security measures imposed by an operating system. Various suitable coprocessors include an additional coprocessor connected to a host processor running the operating system imposing the security measures such as a coprocessor on a add-in card to a computer system, a microcontroller, or a system management mode (SMM) program running on the host processor. The essential utility operates on a computer system having a processor operating under an operating system and a storage. The operating system includes software which limits access to the storage. The utility includes a coprocessor, a software interface and a utility routine. The coprocessor is connected to the storage and operative independent of the operating system for accessing the storage. The software interface is connected to the coprocessor and executes on the processor to control input and output operations on the processor. The utility routine executes on the processor and includes a program code operative via the software interface for activating the coprocessor to access the storage and receiving a response from the coprocessor.

Growing community of inventors

Austin, TX, United States of America

Craig S Jones