Intel Corporation

Apple Inc.

Craig S Forbell

Michael N Derr

Doron Rajwan

Barnes Cooper

Jeffrey R Wilcox

Neil W Songer

Jamie L Langlinais

Avinash N Ananthakrishnan

Soethiha Soe

Jeffrey A Carlson

Jawad Haj-Yihia

Varaprasad V Lingutla

Hardik K Doshi

Joseph J Castro

Ruoying Ma

Gopal Thirumalai Narayanan

Siddharth P Shah

Christopher M Aycock

Xiuting C Mann

An apparatus includes hardware circuits, a front-end power supply, voltage regulators, and control circuitry. The front-end power supply generates electrical power for the hardware circuits. The front-end power supply includes power stages that generate portions of electrical power and are activated and deactivated independently. The voltage regulators are connected to an output of the front-end power supply and provide adjustable operating voltages to the hardware circuits. The control circuitry controls the voltage regulators to supply the adjustable operating voltages responsively to requests from the hardware circuits, compares the adjustable operating voltages to settings that are specified as safe for provisioning by a predefined partial number of the power stages of the front-end power supply, and adaptively activates and deactivates the power stages, including ensuring that a number of active power stages is set to the predefined partial number only while the operating voltages match the safe settings.

System-on-chip with power supply mode having reduced number of phases

A method from managing power state transitions in a computing system is disclosed. A processor may initiate a change in power state from a first initial power state to a first new power state and, in response to initiating the change, send an initial notification to a system integrated circuit using a first communication channel, and deactivate the first communication based on responses to the initial notification. The processor may enter the first new power state in response to the deactivation of the first communication channel, and send a final notification to a management controller using a second communication channel. The management controller may send a message to the system integrated circuit upon receiving the final notification. The system integrated circuit may then transition from a second initial power state to a second new power state based on the message.

Control of power state transitions

Particular embodiments described herein provide for a system, such as a computing system, that includes a processor operable to execute instructions associated with the electronic code, a thermal sensor operable to measure a temperature associated with a device, and a controller in communication with the thermal sensor. The controller is configured to receive an activity status associated with the processor, and receiving a temperature output value representative of a measured temperature associated with the device from the thermal sensor. The controller is further configured to provide a disable signal to the thermal sensor based upon the activity status indicating that the processor is in a reduced activity state and that the temperature output value is less than or equal to a predetermined temperature threshold value.

PCH thermal sensor dynamic shutdown

In an embodiment, a processor includes a plurality of cores and power management logic. The power management logic may be to, in response to a first break event during a reduced power state in the processor, set an exit timer based on a platform latency tolerance, block a first plurality of break events from interrupting the reduced power state, and in response to a expiration of the exit timer, terminate the reduced power state. Other embodiments are described and claimed.

Controlling reduced power states using platform latency tolerance

In an embodiment, the present invention includes a processor having a first domain with at least one core to execute instructions, a second domain coupled to the first domain and having at least one non-core circuit, and a power control unit (PCU) coupled to the first and second domains. The PCU may include a power sharing logic to receive encoded power consumption information from the second domain and to calculate an available power budget for the first domain based at least in part on the encoded power consumption information. Other embodiments are described and claimed.

Sharing power between domains in a processor package using encoded power consumption information from a second domain to calculate an available power budget for a first domain

Systems and methods may provide for monitoring a current provided from a voltage regulator to a non-core region of a processor, and asserting a throttle signal to the non-core region of the processor if the current exceeds a supply capability threshold of the voltage regulator. In one example, a specified current supply capability of the non-core region is greater than a current supply capability of the voltage regulator, and the supply capability threshold is less than the specified current supply capability of the non-core region and an over current protection threshold of the non-core region.

Voltage regulator supplying power exclusively to a non-core region of a processor having a supply capability threshold

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Los Gatos, CA, United States of America

Craig S Forbell