Motorola Corporation

Freescale Semiconductor,inc.

Craig S Amrine

William H Lytle

Clifford L Anderson

Kenneth Andrew Dean

Ronald O Petersen

Owen R Fay

Curtis D Moyer

George R Leal

Jeffery A Whalin

Joyce K Yamamoto

Babu R Chalamala

Peter A Smith

Lizabeth Ann Keser

Scott M Hayes

Zhiwei Gong

Matthew Stainer

Rong-Fong Huang

Victor Adrian Chiriac

Henry G Hughes

Robert Joseph Wenzel

Jianwen Xu

Steven M Smith

Jong-Kai Lin

Wei Gao

Lakshmi Narayan Ramanathan

Charles A Rowell

Scott K Ageno

Arthur J Ingle

Tien Yu T Lee

Thomas Nilsson

Kevin R Lish

Steven Markgraf

Ananda P De Silva

Dave Uebelhoer

Methods for forming electronic assemblies are provided. A device substrate having a plurality of electronic components embedded therein is provided. The device substrate is attached to a carrier substrate using an adhesive material. A plurality of cuts are formed through the device substrate to divide the device substrate into a plurality of portions. Each of the plurality of portions includes at least one of the electronic components. A force is applied to each of the plurality of portions in a direction away from the carrier substrate to remove the plurality of portions from the carrier substrate.

Method for singulating electronic components from a substrate

A method () of packaging integrated circuit (IC) dies () includes applying () a laminating material () to a wafer (), and separating () the wafer () into multiple IC dies () such that the laminating material () is applied to back surfaces () of the IC dies (). Each of the IC dies () is positioned () with an active surface () facing a support substrate (). An encapsulant layer () is formed () overlying the laminating material () and the back surfaces () of the IC dies () from a molding compound (). The molding compound () and the laminating material () are removed from the back surfaces () of the IC dies () to form () openings () exposing the back surfaces (). Conductive material () is placed in the openings () and functions as a heat sink and/or a ground for the IC dies ().

Packaging an integrated circuit die with backside metallization

An assembly for producing partially packaged semiconductor devices is provided. In one embodiment, the assembly includes a magnetic plate; a flexible substrate disposed adjacent the magnetic plate and having two surfaces; a nonstick coating disposed on one surface of the flexible substrate thereby exposing a nonstick surface; and a tape layer having two surfaces. The tape layer is adhesively attached to the nonstick surface to expose a surface of the tape layer. A frame is disposed on the exposed surface of the tape layer, and a plurality of integrated circuit (IC) die is positioned within the frame and supported by the tape layer. A panel is formed within the frame that at least partially surrounds the plurality of IC die and that contacts the tape layer.

Flexible carrier for high volume electronic package fabrication

A method is described for manufacturing electronic assemblies (). Electronic die () held in a plastic matrix () form a partially completed panel () of electronic assemblies (). The panel () is adhesively mounted to a ceramic carrier () having multiple holes () there through. Conductive interconnects (--etc.) and other layers are applied to the panel, coupled to electrical contacts on the die () and external electrical contacts (-) for the panel (). The panel () and the carrier () are separated and the panel singulated to release the finished electronic assemblies (). Silicone is a preferred adhesive () and is dissolved using a non-polar solvent () that penetrates through the holes () in the carrier () to the adhesive (). The adhesive () is preferentially applied using a transfer adhesive sandwich (), that is, an adhesive layer () with removable plastic sheets () on either side that can be peeled away from the adhesive (). This facilitates handling and properly locating the adhesive () on the carrier () for efficient low cost manufacture of the assemblies ().

Electronic assembly manufacturing method

Integrated circuit packages are formed from a panel where the panel is separated by laser cutting the panel. In some embodiments, the panel is attached to the carrier for the formation of interconnect layers on the panel. Afterwards, the panel is cut with a laser while on the carrier to separate the integrated circuit packages. A tape or other type of structure may be attached to the top of the packages after the laser cutting. The integrated circuit packages are removed from the carrier by releasing the adhesive and removing the integrated circuit packages with the tape. The packages are then removed from the tape.

Integrated circuit package formation

Methods and apparatus are provided for use in manufacturing a device packaging comprising the steps of: positioning a metal substrate such as spring steel on a magnetic plate so as to expose a surface of the metal substrate; placing a first tape layer on the exposed surface of a metal substrate so as to expose a nonstick surface of the first tape layer such as PTFE; placing a second tape layer on the exposed surface of the first tape layer so as to expose a surface of the second tape layer; positioning a mold frame on the exposed surface of the second tape layer; positioning a die within the mold frame; depositing epoxy within the mold frame; curing the epoxy so as to create a molded panel; removing the mold frame; grinding the molded panel to a desired thickness; separating the first tape layer from the second tape layer so as to separate the metal substrate from the molded panel; and peeling the second tape layer from the molded panel. The process provides an efficient method for creating a chips first package.

Flexible carrier and release method for high volume electronic package fabrication

A multi-layer structure () includes a first build-up layer structure () configured to connect to a heat-generating module (), a second build-up layer structure () configured to connect to a substrate, and a middle layer () provided between the first build-up layer structure and the second build-up layer structure, the middle layer including at least one semiconductor component () and a heat spreader (). A first set of thermal vias () extend through the first build-up layer structure to the heat spreader, and a second set of thermal vias (extend through the second build-up layer structure to the heat spreader, wherein at least a portion of the first set of thermal vias is in thermal contact with the heat-generating module.

Methods and apparatus for thermal management in a multi-layer embedded chip structure

A process for encapsulating an integrated circuit die () using a porous carrier (). In one example, an adhesive structure (e.g. tape) is applied to a porous carrier. Integrated circuit die is then placed on the adhesive structure. The integrated circuit die is then encapsulated to form an encapsulated structure (). The carrier is then subjected to a solvent that passes through the carrier to reduce the adhesive strength of the adhesive structure for removal of the carrier from the encapsulated structure.

Die encapsulation using a porous carrier

An exemplary method and apparatus for MEMS device wafer level and/or array packaging comprises inter alia an EM shielding array of dielectric lid elements () sealed to a MEMS device die array () to produce a sealed MEMS device package array (). Disclosed features and specifications may be variously controlled, adapted or otherwise optionally modified to improve hermetic sealing and/or EM shielding for any MEMS device. An exemplary embodiment of the present invention representatively provides for wafer level packaging of RF MEMS switches prior to device singulation.

Wafer level MEMS packaging

A method of fabricating a high vacuum display with flat form factor, and the display, include an envelope with two major, parallel spaced apart glass sides and a continuous edge therebetween. An opening is formed through one of the glass sides of the envelope. A plate is provided with an area larger than the opening in the envelope. A button with an area slightly smaller than the opening may be formed on one side of the plate. A low temperature melting material is positioned on the plate around the button and the envelope is positioned in a substantial vacuum. The button is placed in the opening with the plate abutting the glass side outside of the envelope and the low temperature melting material is melted using heat and/or pressure to sealingly engage the button within the opening.

Seal and method of sealing devices such as displays

A method for fabricating a field emission display ( ) includes the steps of providing a cathode plate ( ), providing an anode plate ( ), providing a spacer substrate ( ) made from a bulk spacer material ( ), cutting the spacer substrate ( ) to define a spacer ( ) having a surface ( ), passivating the surface ( ) of the spacer ( ) using the bulk spacer material ( ) to form a passivation layer, and disposing the spacer ( ) between the cathode plate ( ) and the anode plate ( ). A field emission display ( ) which includes a cathode plate ( ) having a plurality of electron emitters ( ), an anode plate ( ) opposing the cathode plate ( ), and a spacer ( ) extending between the cathode plate ( ) and anode plate ( ). The spacer ( ) has a passivation layer made from bulk spacer material ( ).

Method for fabricating a field emission display having a spacer with a passivation layer

A field emission display (400) includes a cathode plate (410), an anode plate (430), and a mechanical support/getter assembly (300) being disposed between the cathode plate (410) and the anode plate (430). The mechanical support/getter assembly (300) includes a unitary spacer/frame assembly (310) made from a photosensitive glass. A method for fabricating the mechanical support/getter assembly (300) includes the steps of: selectively exposing inter-spacer regions (110) and a getter frame region (120) of a layer (100) of the photosensitive glass to UV radiation, heating the layer (100) to crystallize the UV-exposed regions, and removing the crystallized inter-spacer regions (110) and partially removing the crystallized getter frame regions by contacting the layer (100) with an acid, thereby forming spacer ribs (314) and a getter land (322). The method further includes providing a getter frame (320) on the spacer land (322).

Method of making field emission display having a mechanical

A field emission device (400) includes a plastically-deformable, ceramic, stamped substrate (200) made from a plastically deformable ceramic, which in the preferred embodiment includes a calendered tape. The plastically-deformable, ceramic, stamped substrate (200) includes first and second opposed surfaces (202, 204) and defines apertures (206) in which are formed extraction electrodes (410). The field emission device (400) further includes an electron-emissive layer (418) being formed on the first opposed surface (202). Cathodes (420) are disposed on the electron-emissive layer (418) and cross the extraction electrodes (410) at an angle of 90.degree.. A method for fabricating said field emission device (400) includes stamping a layer (100) of the softened calendered tape with a die (300) to define the apertures (206) and grooves (208, 212, 214).

Field emission device having stamped substrate and method

A method for affixing spacers (126, 226, 326) in a field emission display (100, 200, 300) includes the steps of: (i) providing a first display plate; providing a plurality of spacers (126, 226, 326) having first (128, 228, 328) and second opposed edges (130, 230, 330), (ii) coating first opposed edge (128, 228, 338) with a bonding layer (132, 232, 332), (iii) forming a metallic bonding pad (134, 234) on an inner surface (106, 206, 306) of first display plate, and (iv) applying a energy beam (136, 236, 336) to the bonding layer (132, 232, 332) and metallic bonding pad (134, 234), thereby forming a metallic bond.

Method for affixing spacers in a field emission display

A field emission display (100) includes a cathode plate (102) having a plurality of electron emitters (124), an anode plate (104) opposing the cathode plate (102), and a bulk-resistive spacer (108) extending between the anode plate (104) and the cathode plate (102). The bulk-resistive spacer (108) is made from an electrically conductive material. The resistivity of the electrically conductive material is selected to remove impinging charges while preventing excessive power loss due to electrical current through the bulk-resistive spacer (108) from the anode plate (104) to the cathode plate (102).

Growing community of inventors

Tempe, AZ, United States of America

Craig S Amrine