Radian Memory Systems, Inc.

Other

Datadirect Networks, Inc.

Teradyne, Inc.

Radian Memory Systems, Illc

Craig Robertson

Robert Lercari

Mike Jadon

Andrey V Kuzmin

Alan Chen

Joshua D Abbey

Dan Olster

Jan Olderdissen

Doug Schafer

Dave Fellinger

Raphael Davis

Raphael P Davis

George W Conner

Peter A Reichert

This disclosure provides techniques hierarchical address virtualization within a memory controller and configurable block device allocation. By performing address translation only at select hierarchical levels, a memory controller can be designed to have predictable I/O latency, with brief or otherwise negligible logical-to-physical address translation time. In one embodiment, address transition may be implemented entirely with logical gates and look-up tables of a memory controller integrated circuit, without requiring processor cycles. The disclosed virtualization scheme also provides for flexibility in customizing the configuration of virtual storage devices, to present nearly any desired configuration to a host or client.

Hierarchical storage device with host controlled subdivisions

This disclosure provides a memory controller for asymmetric non-volatile memory, such as flash memory, and related host and memory system architectures. The memory controller is configured to automatically generate and transmit redundancy information to a destination, e.g., a host or another memory drive, to provide for cross-drive redundancy. This redundancy information can be error correction (EC) information, which is linearly combined with similar information from other drives to create 'superparity.' If EC information is lost for one drive, it can be rebuilt by retrieving the superparity, retrieving or newly generating EC information for uncompromised drives, and linearly combining these values. In one embodiment, multiple error correction schemes are used, including a first intra-drive scheme to permit recovery of up to x structure-based failures, and the just-described redundancy scheme, to provide enhanced security for greater than x structure-based failures.

Erasure coding techniques for flash memory

A host stores 'context' metadata for logical block addresses (LBAs) in a manner tied to physical location. Notwithstanding log-structured or copy on write processes, the host is then provided with immediate context when the host is called upon to assist a memory controller with data identified by physical location, for example, for memory reconfiguration, garbage collection, wear leveling or other processes. The metadata for example can provide the host with insight as to which data may be moved to enhance performance optimization and where that data can be placed. In one embodiment, the host writes back one or more references that span multiple layers of indirection in concert with write of the underlying data; in another embodiment, the context can point to other metadata.

Techniques for directed data migration

Processing functions are offloaded to a memory controller for nonvolatile memory by a host in connection with write data. The nonvolatile memory executes these functions, producing processed data that must be written into memory; for example, the offloaded functions can include erasure coding, with the nonvolatile memory controller generating redundancy information that must be written into memory. The memory controller holds this information in internal RAM and then later writes this information into nonvolatile memory according to dynamically determined write time and/or destinations selected by the host, so as to not collide with host data access requests. In one embodiment, the memory is NAND flash memory and the memory controller is a cooperative memory controller that permits the host to schedule concurrent operations in respective, configurable virtual block devices which have been configured by the host out of a pool of structural flash memory structures managed by the memory controller.

Nonvolatile memory controller with delegated processing

Nonvolatile memory controller supporting variable configurability and forward compatibility

Storage deveice that garbage collects specific areas based on a host specified context

Storage device with division based addressing to support host memory array discovery

A package has a plurality of seamless compartments coupled together. A different one of the plurality compartments each includes a different respective one of a plurality of respective void spaces and a different respective one of a plurality of respective void space delimiting surfaces. A different one of a plurality of fill entries each forms a fluent entry into a different respective compartment's void space. At least one fill entry of said plurality is in an elastomeric portion of said package, and the at least one fill entry has a largest cross sectional area which is equal to or less than 25% of a largest cross sectional area of the compartment having the respective void space for which the fill entry forms the fluent entry. Each void space delimiting surface follows an outline of a separate 3D pill shape.

Package for frozen nutrient pill

Storage drive with NAND maintenance on basis of segments corresponding to logical erase units

Storage drive with defect management on basis of segments corresponding to logical erase units

Storage system with division based addressing and query based cooperative flash management

Storage system with division based addressing and cooperative flash management

Techniques for supporting erasure coding with flash memory controller

Growing community of inventors

Simi Valley, CA, United States of America

Craig Robertson