International Business Machines Corporation

Craig R Selinger

Timothy A Schell

Kenneth Lee Christian

Michael A Granato

Wiren Dale Becker

Gerard M Salem

Bradley David McCredie

George A Katopis

Charles Kyriakos Vakirtzis

Matthew Edward Aubertine

Kianoush Beyzavi

Michael Herasimtschuk

Ronald P Checca

Harold J Broker

David A Haeussler

Michael J Jurkovic

Michael Lee Hackett

Paul R Zehr

Jerome R Relis

Cynthia L Martin

Gregory F Miceli

Hardev S Dhaliwal

Vernon L Watts

Hope L Bauer

Deepak D Sherlekar

Gerald W Mahoney

For a station in a data communication network having a predefined limit of congestion for handling data immediately undergoing transmission through the station, a system for improving service given to network users requesting new access services to support new transmissions through the same station while the predefined congestion limit is exceeded. This system contains: a first element for determining when the predefined limit is exceeded by existing data transmissions through the station; and a second element, responsive to requests for new access services that are received while the predefined limit is being exceeded for: concurrently processing the request for new service and reducing the quality of service (QoS) to selected users. The reductions in QoS generally have the effects of reducing the speed/priority of handling of data being transmitted to or from the selected users, and of freeing up of sufficient bandwidth to accommodate the requested new access services. The system includes a third element for restoring/upgrading QoS, to users whose QoS has been reduced, when bandwidth usage subsides to a level allowing for such restoration. This latter level is sufficiently less than the congestion limit to provide a hysteresis effect that delays actions by the third element sufficiently to prevent successive actions of said second and third elements from producing unstable fluctuations in the operation of the station. Arrangements are disclosed for applying the invention in a cable television network environment and in private network environments serving a single business enterprise such as a banking institution.

Improving access to congested networks

An anticipation of engineering changes to a multiple-level integrated circuit package, resulting in a significant decrease in the turnaround time required to make engineering changes. After the first pass of the design phase is complete and before manufacture has begun, surplus I/O at different package levels are wired into surplus connections involving all but the highest package level. These surplus connections are reserved for future use when engineering changes become necessary. Once manufacture is complete, the surplus connections can be converted into logical connections by ECing only the highest packaging level with the quickest turnaround time. The surplus connections also provide a means for implementing ongoing incremental engineering changes as they are needed.

Method for facilitating engineering changes in a multiple level circuit

A method of wiring a plurality of integrated circuits within a chip or between chips in one or more packages by adding cluster points to a net that includes a plurality of nodes to be interconnected. The interconnected nodes are designed to meet system requirements, commonly expressed by a set of wiring rules, include among others, physical, electrical and noise constraints. The method includes matching interconnection net attributes to wiring rule logical definitions, wherein the wiring rules include rule nodes and rule connections. The rule nodes define constraints for the pins, vias and cluster point structures. The rule connections define wiring constraints between the node structures to establish the net topology. The process described is based on net ordering and checking. The net ordering, which defines the pin-to-pin connections based on the wiring rule, is performed prior to chip or package wiring. Net ordering imposes the wiring rule added cluster points, the desired interconnection topology and the wiring constraints to the net. Checking verifies the correctness of the net attributes when the design wiring is complete.

Method of adding constrained cluster points to interconnection nets in

Disclosed is a method and system for removing hardware overlap for use with a computer aided design apparatus. The method and system remove overlap by separately classifying all free blocks and blocks fixed in place, and then shifting cells between free blocks while maintaining the same relative ordering of the cells. Thus, all move bounds are respected and only cells that exist in free blocks actually move. The operation takes place one partition at a time, whereby a typical partition includes a row of cells.

Method and system for removing hardware design overlap

Permutations of orders of elements such as electrical connection pins, vias and t-junctions at known locations are efficiently tested against at least type and distance criteria by forming a plurality of lists of the elements and screening the elements of each list against respective ones of said type criteria to reduce the length of the lists of elements. Pointers to ones of the distance criteria and remaining members of a list corresponding to respective ones of the distance criteria iteratively form pairs of elements which are checked for separation. When the check fails or a solution is found, the pointer to list members is advanced. The pointer to respective distance criteria is advanced when a check is successful. When a list is exhausted and a check is unsuccessful, the pointer to respective distance criteria is regressed. Advancement and regression of pointers reduces iterations of combinations of pairs of elements which do not lead to a solution in order to accelerate the process. Each new solution is evaluated against a single stored prior solution for optimization of solutions while greatly reducing storage requirements.

Method and apparatus for dynamically varying net rules

A method is provided to assign component I/O (input/output, the interface area between levels of physical packaging) pins for all components at each level of the computer system. In a hierarchical, top-down design methodology, the I/O pins for each computer system component are assigned to nets (a net is an interconnection of pins on a level of packaging, or between levels of packaging) based on wire length, electrical limits and timing. Parameters that are considered are net priority (the importance of this net to the system, relative to other nets in the system), location of physical components, location of physical component I/Os at all computer system levels of physical packaging hierarchy, and I/O pin characteristics. An iterative method is used to assign and reassign I/O pins at each level based on timing. As I/Os are reassigned at each lower component level, new assignments are made at all higher levels of the system packaging hierarchy based on the changed parameters at the lower level. I/Os assignment by this method for a computer system package design reduces the occurance of any critical nets failing length, electrical or timing constraints due to poor I/O assignments. The method has built in checks to avoid being trapped in an NP complete situation (a form of endless loop).

Method of I/O pin assignment in a hierarchial packaging system

A method for minimizing the time skew between signals traveling through various multi-cycle path nets linking one or several VLSI packages that includes a plurality of IC chips interconnected to each other. The method includes equalizing differences between the early and the late mode slack for each of the multi-cycle nets to decrease the joint probability of failure; maximizing the time balance between the early and the late mode slack; balancing over all the nets the difference between the early and the late mode slack, minimizing in the process statistical variations within the mode slack pair; and compensating for asymmetries between rising and falling switching times using the mode slack pair. The method allows multi-cycle path nets have their transmission line length confined between a maximum and a minimum length, which in turn minimizes the skew between signals in each of the nets, decreases cycle time and .improves the overall performance of the system.

Method for minimizing the time skew of electrical signals in very large

Switching characteristics of system components are represented and summed so that their effects on the overall system can be observed during the design process. Full simultaneous switching analysis is provided at the earliest levels of design containing minimal level of design data by a method of computing net based simultaneous switching noise levels which supports packages ranging from the smallest chip level to the largest board level. The simultaneous switching activity is computed based on interaction between each driver and each other driver between each component and each other component, with consideration to the spatial inter-relationship net, within a higher level component, to determine each component's drivers effect on itself as well as the coupling effect between drivers on different components. The analysis involves computing simultaneous switching noise by associating a characteristic triangle with each driver application configuration. The characteristic triangle. The height of the triangle, as well as the pitch of the sides of the triangle will be determined by the characteristics of the net. In the early stages of design, a default characteristic triangle is defined for each technology type. A general triangle is also defined for cases where early analysis needs to be performed prior to choosing a technology.

Early high level net based analysis of simultaneous switching

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Spring Valley, NY, United States of America

Craig R Selinger