Unisys Corporation

Craig R Church

Andrew T Jennings

Duane J McCrory

Joseph S Schibinger

Laurence P Flora

Timothy Neilson Fender

Jospeh S Schibinger

A method for communicating active messages among nodes of a parallel processing computer system is disclosed. The active messages are defined by .mu.threads, and the method comprises the steps of: (a) generating a .mu.thread comprising an instruction pointer, frame pointer, and Local Parameters pointer from a first node to a second node; and (b) performing a procedure on a data structure in accordance with the .mu.thread. The instruction pointer points to an application specific procedure in system memory, and the frame pointer points to an application specific data structure in system memory. The Local Parameters pointer points to one or more words of additional data or parameters stored in memory mapped device registers or system memory.

Methods and apparatus for exchanging active messages in a parallel

A low latency software and hardware interface between a microprocessor and Network Interface Unit is disclosed. The Network Interface Unit interfaces to the microprocessor's Level 2 cache interface, which provides burst transfers of cache lines between the microprocessor and Network Interface Unit. The Network Interface Unit is memory mapped into the microprocessor's address space. Two memory mapped cache lines are used to write commands to the Network Interface Unit's Write Window and another two cache lines are used to read results of the commands from the Network Interface Unit's Read Window. The Write Window is a three port register file. Data is written into one write port and read simultaneously from two read ports. One read port is used during read operations to the Write Window while the other is used during command execution to move data to the Internal Structures block. The Read Window is a 2-1 multiplexor that is 128 bits wide. On a read operation data may be selected from the Write Window or the Internal Structures.

Low latency message processor interface using memory mapped Read/Write

A block structured data processing system concatenates block structured code so as to expedite the execution of less structured language code. The concatenation is performed in a code unit for a parallel pipeline processor so that the concatenated code can be executed in parallel. To optimize the access to the data associated with address couples, an address couple associative memory (ACAM) is provided for the translation of conventional address couples found in block structured systems into general registers numbers. The mechanism attempts to keep data in the general registers thus removing the requirement to re-fetch it from the memory system. To expedite the fetching of data arrays, descriptors may be stored in ACAM for use in continuously accessing data arrays in memory.

Method and means for concatenating multiple instructions

A computer system executes steps to provide results in an order different from an intended order. Instructions are concatenated into a plurality of jobs. Different invocations of a variable within the computer instruction stream may be assigned respectively different storage locations and each storage location may correspond to a different job. When all the storage locations associated with a particular job indicate available resources (e.g. valid variable input), the job may be executed. A mechanism allows for job re-execution, if needed, due to interrupt or error.

Growing community of inventors

Havertown, PA, United States of America

Craig R Church