Exar Corporation

Other

National Semiconductor Corporation

Integrated Device Technology, Inc.

Craig N Lambert

Kent Kernahan

John Carl Thomas

Sorin Andrei Spanoche

Ronald W Russell

Anton Bakker

Jasleen M Raisinghani

A wireless power enabled apparatus may comprise a wireless power receiver that includes a receive coil configured to generate an AC signal responsive an electromagnetic field, a rectifier including a plurality of switches configured to receive the AC signal and generate an output power signal, and control logic configured to control the plurality of switches to cause the rectifier to modulate the output power signal. The control logic may be configured to control the plurality of switches within the rectifier to have an overlap delay that modulates at least one parameter of the wireless power receiver. A method of operating a receiver side of a wireless power transfer system comprises generating an output power signal including a rectified voltage and a rectified current responsive to receiving a wireless power signal, and controlling a rectifier according to at least one mode including a power modulation mode modulating the output power signal.

Apparatuses and related methods for modulating power of a wireless power receiver

A voltage signal is monitored in comparison to another voltage signal by a differential amplifier. When the first voltage signal value drops below the second voltage signal value an output signal is boosted in response. The output signal returns to a previous state without boost.

Low power method of responsively initiating fast response to a detected change of condition

Electrical components which substantially dissipate the power provided them in the form of heat will change temperature in response to self heating, heat transfer to their surroundings, and heat transferred from one component to another. A method is disclosed for calculating the temperature of a component(s) using a thermal model. In one embodiment the power dissipation of each component is controlled to limit the temperature of the component. In one embodiment the temperature of a component is modified by changing the power dissipation of another component. In some embodiments the power dissipation of a component is modified by modifying its performance. In another embodiment power dissipation is modified by selecting one or more programs for modified execution.

Model predictive thermal management

A synchronous control system includes a logic controller (e.g., microprocessor) which can be put into low power standby or sleep mode by shutting off its clock. A quick-start oscillator (QSO) remains shut off to conserve power when not needed, but awakens rapidly and supplies clock signals to the logic controller for quickly awakening the controller so the latter can to respond to exigent circumstances. One such circumstance can be the drop of a vital supply voltage below a predefined threshold. A low power comparator (LPTC) detects the drop and starts up the QSO which in turn awakens the controller. The controller determines what the reason for the awakening is, quickly responds to the exigent circumstance and then turns the QSO off to thereby conserve power and put itself (QSO) back to sleep. Disclosures are provided for the QSO and a first calibration subsystem used to maintain QSO output frequency within a desired range. Disclosures are provided for the LPTC and a second calibration subsystem used to set its trigger threshold. Disclosure of a novel DAC within the LPTC is also provided.

Low power method of monitoring and of responsively initiating higher powered intelligent response to detected change of condition

A voltage level converter circuit is presented that is capable of independently adjusting the falling edge and rising edge delays of the output signal. The circuit includes two separate transconductance amplifiers each biased independently. Each one of the transconductance amplifiers separately drives an output transistor. The circuit is particularly suited for converting ECL signals to CMOS logic levels.

Voltage level converter with independently adjustable rise and fall

A circuit technique for improving power supply rejection of current mirror circuits having multiple outputs. An input reference current is preadjusted for error caused by power supply variations and then mirrored through a cascade of current mirror circuits. In one embodiment an opamp loop forces the output of a current mirror circuit to be substantially equal to the reference current. This current is then used in subsequent mirroring stages to obtain various outputs. The circuit eliminates the need for including an error-subtraction transistor at every output.

Low-voltage multi-output current mirror circuit with improved power

A circuit technique for improving power supply rejection of current mirror circuits. An input reference current is mirrored through a cascade of current mirror circuits whereby an error current is generated that represents the amount of current variation caused by power supply variations. The error current is then replicated into a current summing circuit which cancels out the effect of the error current. The output current is thus substantially independent of power supply variations.

Low-voltage cascaded current mirror circuit with improved power supply

A post-assembly trim of a monolithic IC is set forth wherein selected package pins can be employed to address the on-chip trim circuit. Then, after the trim is completed, the circuit is addressed to provide a disconnect of the coupling between the trim pins and the post assembly trim circuit of the IC, while leaving the pins fully usable for other purposes. This means that following the post-assembly trim the trim pins cannot accidentally be employed for further trimming and the packaged IC is user-proof. A circuit that employs zener zapping for both trimming and disconnect is detailed and the invention is clearly usable for plastic encapsulated devices. However, when cavity containing packages are involved it is shown that a combination of zener zapping and fuse blowing can be employed.

User-proof post-assembly offset voltage trim

A trim arrangement for adjusting a differential input stage in a BIFET.RTM. integrated circuit is presented wherein the trimming is done at wafer probing in the manufacturing process. Trim JFETs are invoked by means of reverse biased zener diodes which can be zapped thereby to achieve trimming in the conventional manner. The trim JFETs are ratioed in size so that the trim is V.sub.P compensated over a relatively broad range. An improved trim structure is presented wherein the offset trim is V.sub.P compensated and operated in a manner that renders its effect on the circuit constant and independent of the conventional load trim.

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San Jose, CA, United States of America

Craig N Lambert