Syndiant Inc.

Xdmicro(zhongshan) Optoelectronics Semiconductor Co. Ltd

Hpl Technologies, Inc.

Syndiant, Inc. & Xdmicro(zhongshan) Optoelectronics Semiconductor Co. Ltd

Craig Michael Waller

Andrew Ian Russell

Eric Paul Eisenbrandt

Karl M Guttag

Joshua Lund

Chun Chiu Daniel Wong

James E Howard

Jason Stevens

Daran DeShazo

Agustinus Sutandi

Timothy Randall Rost

A display with multiple light sources sharing a device driver is disclosed. In one embodiment of the present invention a display includes a first device driver, a first light source, a second light source and a first light-source selection circuit which is coupled to the first device driver, the first light source and the second light source. The first light-source selection circuit is configured to pair the first device driver with the first light source during a first time interval and to pair the first device driver with the second light source in a second time interval.

Display backplane with shared drivers for light source

Display backplane with shared drivers for light source devices

Display Pixel Design and Control for Lower Power and Higher Bit Depth Craig Michael Waller A method to generate pixel control signals more rapidly and with less overhead is disclosed. The method generates pixel control signals for a first block of pixels having a first first-block pixel and a second first-block pixel and a second block of pixels having a first first-block pixel and a second second-block pixel. A first-block base control signal that is shared by the first block of pixels is generated. A first first-block sharpening control signal for the first first-block pixel is generated and a first second-second-block sharpening control signal for the first second-block pixel is generated. The first first-block pixel control signal is generated using the first first-block sharpening signal and the first-block base control signal. The first second-block pixel control signal is generated using the first second-block sharpening signal and the second-block base control signal.

Display pixel design and control for lower power and higher bit depth

A method to generate pixel control signal more rapidly and with less overhead is disclosed. The method generates pixel control signals for a block of pixels having a first pixel and a second pixel. A base control signal that is shared by the block of pixels is generated. A first sharpening control signal for the first pixel is generated and a second sharpening control signal for the second pixel is generated. The first pixel control signal is generated using the first sharpening signal and the base control signal. The second pixel control signal is generated using the second sharpening signal and the base control signal. The base control signal is stored in a first memory cell; the first sharpener control signal is stored in a second memory cell; and the second sharpener control signal is stored in a third memory cell.

A method to generate a quad-quincunx video stream is disclosed. The method generates a quad-quincunx video stream from a high resolution video stream by generating a first first-type quincunx field from a first high resolution video frame, a first second-type quincunx field from a second high resolution video frame, a first third-type quincunx field from a third high resolution video frame, and a first fourth-type quincunx field from a fourth high resolution video frame.

Generating quincunx video streams for light modulating backplanes with configurable multi electrode pixels

A method to generate a quincunx video stream is disclosed. The method includes generating a first-type quincunx field from a first high resolution video frame. The first-type quincunx field has a plurality quincunx pixels, each of which has an associated pixel in the first high resolution video frame. The quincunx pixels are calculated using a smoothing filter and a pixel block containing the associated pixels and other high resolution pixels near the associated pixels. A second-type quincunx field is generated from a second high resolution video frame.

A light modulating Backplane with configurable multi-electrode pixels is disclosed. The configurable multi-electrode pixel includes a first set of dot electrodes in a first field and a second set of dot electrodes in a second field. Generally, dot electrode is included in both the first set of dot electrodes and the second set of dot electrodes. For example, a pixel control circuit coupled to a dedicated dot electrode. A first dot electrode is coupled to the pixel control circuit by a first dot electrode connection circuit and a second dot electrode is coupled to the pixel control circuit by a second dot electrode connection circuit. During the first field the first dot electrode connection circuit is active while the second dot electrode connection circuit is inactive. During the second field, the first dot electrode connection circuit is inactive while the second dot electrode connection circuit is active.

Light modulating backplane with configurable multi-electrode pixels

Described are devices and methods for reducing the need for storage on a display panel, for reducing the required bandwidth to a display panel, for increasing the light-on time for a display panel.

Spatial light modulator with storage reducer

Described is a device comprising a spatial light modulator comprising a plurality of comparators for computing a respective drive for each pixel of a plurality of pixels.

Spatial light modulator with masking-comparators

A low standby current power-on reset circuit is described. A first NMOS transistor's drain is coupled to a first PMOS transistor's drain; source coupled to ground line; and gate coupled to a first capacitor coupled to ground line. The first PMOS transistor's source is coupled to power line; gate coupled to second capacitor coupled to ground line; and drain provides a power-on reset indication. A second PMOS transistor's source is coupled to power line; drain is coupled to drain of second NMOS transistor, gates of first PMOS, second PMOS, and second NMOS transistors, and second capacitor. The second NMOS transistor's source is coupled to gate of first NMOS transistor and first capacitor. A discharge circuit is coupled to power line, ground line, and first and second capacitors for discharging the capacitors when a voltage on power line drops below a level determined by the second PMOS transistor's threshold voltage.

Growing community of inventors

Dallas, TX, United States of America

Craig Michael Waller